Methods and apparatus for managing connections between multiple internal integrated circuits (ICs) of, for example, a high-speed internal device interface. Improved schemes for coordination of connection and disconnection events, and/or suspension and resumption of operation for a High-Speed Inter-Chip (HSIC) interface are disclosed. In one exemplary embodiment, a device-initiated and host-initiated connect/disconnect procedure is disclosed, that provides improved timing, synchronization, and power consumption.

Programmable devices, hierarchical parallel machines and methods for providing state information are described. In one such programmable device, programmable elements are provided. The programmable elements are configured to implement one or more finite state machines. The programmable elements are configured to receive an N-digit input and provide a M-digit output as a function of the N-digit input. The M-digit output includes state information from less than all of the programmable elements. Other programmable devices, hierarchical parallel machines and methods are also disclosed.

Apparatus adapted for exascale computers are disclosed. The apparatus includes, but is not limited to at least one of: a system, data processor chip (DPC), Landing module (LM), chips including LM, anticipator chips, simultaneous multi-processor (SMP) cores, SMP channel (SMPC) cores, channels, bundles of channels, printed circuit boards (PCB) including bundles, floating point adders, accumulation managers, QUAD Link Anticipating Memory (QUADLAM), communication networks extended by coupling links of QUADLAM, log 2 calculators, exp2 calculators, log ALU, Non-Linear Accelerator (NLA), and stairways. Methods of algorithm and program development, verification and debugging are also disclosed. Collectively, embodiments of these elements disclose a class of supercomputers that obsolete Amdahl's Law, providing cabinets of petaflop performance and systems that may meet or exceed an exaflop of performance for Block LU Decomposition (Linpack).

Methods and apparatus for managing connections between multiple internal integrated circuits (ICs) of, for example, a high-speed internal device interface. Improved schemes for coordination of connection and disconnection events, and/or suspension and resumption of operation for a High-Speed Inter-Chip (HSIC) interface are disclosed. In one exemplary embodiment, a device-initiated and host-initiated connect/disconnect procedure is disclosed, that provides improved timing, synchronization, and power consumption.

An interconnection system comprising a plurality of nodes, each comprising at least two ports, and a plurality of links configured to interconnect ports among the nodes to form a hierarchical multi-level ring topology, wherein the ring topology comprises a plurality of levels of rings including a base ring and at least two hierarchical shortcut rings, and wherein each node connected to a higher-level shortcut ring is also connected to all lower-level rings including the base ring.

A system and method for network switching is provided. A plurality of processing modules is accessed and each processing module includes a plurality of processing nodes. Each processing node is associated with an intra-module port and an inter-module port. At least a portion of the processing nodes are connected within each processing module via the intra-module ports. A ring of the processing modules is formed via inter-module connections between a portion of the inter-module ports of the processing modules. One of the processing nodes of at least a portion of the processing modules is connected with a network switch.

A system and method for making and using a computing system framework with unified storage, processing, and network switching fabrics are provided. Processing nodes, either physical or virtual, are associated with intra-module ports, inter-module ports, and local storage spaces. A plurality of processing nodes are linked through intra-module ports to form processing modules. A plurality of the processing modules are connected through inter-module ports to form the computing system. Network switch can be incorporated into intra-module or inter-module connections. Several inter-module connection schemes, which can be adapted to use with existing network packet routing algorithms, are disclosed. Each processing node needs only to keep track of the states of its directly connected neighbors, obviating the need for a high-speed connection to the rest processing nodes within the system. Dedicated network switching equipment can be flexibly employed and network capacity grows naturally as processing nodes are added.

A plurality of software programmable processors is disclosed. The software programmable processors are controlled by rotating circular buffers. A first processor and a second processor within the plurality of software programmable processors are individually programmable. The first processor within the plurality of software programmable processors is coupled to neighbor processors within the plurality of software programmable processors. The first processor sends and receives data from the neighbor processors. The first processor and the second processor are configured to operate on a common instruction cycle. An output of the first processor from a first instruction cycle is an input to the second processor on a subsequent instruction cycle.

Systems and methods to be used by a processing element from among multiple computing resources of a computing system, where communication between the computing resources is carried out based on network on a chip architecture, to send first data from memory registers of the processing element and second data from memory of the computing system to a destination processing element from among the multiple computing resources, by sending the first data to a memory controller of the memory along with a single appended-read command.

Methods and apparatus for managing connections be multiple internal integrated circuits (ICs) of for example, a high-speed internal device interface. Improved schemes for coordination of connection and disconnection events, and/or suspension and resumption of operation for a High-Speed Inter. Chip (HSIC) in are disclosed. In one exemplary embodiment, a device-initiated and host-initiated connect/disconnect procedure is disclosed, that provides improved dining, synchronization, and power consumption.