An integrated circuit, and a data processing device and method are provided. The integrated circuit includes a processor circuit and an accelerator circuit. The processor circuit includes a processor, a first data storage section, and a first data input/output interface. The accelerator circuit includes an accelerator and a second data input/output interface. The second data input/output interface is electrically connected to the first data input/output interface, so that the accelerator circuit can perform information interaction with the first data storage section.

A system including a plurality of processor cores, a plurality of graphics processing units, a plurality of peripheral circuits, and a plurality of memory controllers is configured to support scaling of the system using a unified memory architecture.

In an embodiment, a system contains a network testing engine that sends test data along different paths of a network between a source and a destination, wherein each path contains a plurality of network nodes, and receives, in response to sending the test data, response data about the paths. The system further contains a network path characteristics engine that determines characteristics of each path based on the response data, and a delivery parameters engine that receives a request for delivery of a data load from the source to the destination and determines, based on the request, delivery parameters. Furthermore, the system contains the source and a path selection engine that determines a selected path of the different paths based on the characteristics of the paths and the delivery parameters, and sends the selected data path to the source, which sends the data load along the selected path to the destination.

A system including a plurality of processor cores, a plurality of graphics processing units, a plurality of peripheral circuits, and a plurality of memory controllers is configured to support scaling of the system using a unified memory architecture.

A system including a plurality of processor cores, a plurality of graphics processing units, a plurality of peripheral circuits, and a plurality of memory controllers is configured to support scaling of the system using a unified memory architecture.

In some implementations, a device may cause a single host device to load data to a first memory device of a plurality of memory devices configured in a fabric. The device may cause the first memory device to propagate the data to one or more second memory devices, of the plurality of memory devices, via one or more peer-to-peer transfer operations to replicate the data from the first memory device to the one or more second memory devices without involvement of the single host device.

A high-performance computing system having at least one computational group of at least one core, each computational group being associated with a computational memory, arranged to form a computational resource being utilized for performing computations, a concierge module with at least one concierge group of at least one core associated with a concierge memory arranged to form a reserved support resource being utilized for performing support functions to said computational resource. The computational resource is coupled to the concierge module through a cache coherent interconnection to maintain uniformity of shared resource data that are stored in the computational memory and concierge memory so that the high-performance computing system is functionally transparent to a software code runs on the computational group, and the cores in the computation and concierge groups are interchangeable for the software code such that the cores are used for performing any one of computations or support functions, and the cores use any one of the computational and concierge memory.

A system including a plurality of processor cores, a plurality of graphics processing units, a plurality of peripheral circuits, and a plurality of memory controllers is configured to support scaling of the system using a unified memory architecture.

Techniques are disclosed related to a scalable system on a chip (SOC). In some embodiments, a system includes a plurality of processor cores, a plurality of graphics processing units, a plurality of peripheral circuits, and a plurality of memory controllers configured to support scaling of the system using a unified memory architecture.