A multi-core processor providing heterogeneous processor cores and a shared cache is presented.

The present disclosure relates to low-layer memory for a computing platform. An example embodiment includes a memory hierarchy being directly connectable to a processor. The memory hierarchy includes at least a level 1, referred to as L1, memory structure comprising a non-volatile memory unit as L1 data memory and a buffer structure (L1-VWB). The buffer structure includes a plurality of interconnected wide registers with an asymmetric organization, wider towards the non-volatile memory unit than towards a data path connectable to the processor. The buffer structure and the non-volatile memory unit are arranged for being directly connectable to a processor so that data words can be read directly from either of the L1 data memory and the buffer structure (L1-VWB) by the processor.

The present application discloses a mainboard, a processor board card, and a computing system. The mainboard includes a plurality of interfaces, a first interface of the plurality of interfaces is configured to be connected to the processor board card having a processor circuit, a second interface of the plurality of interfaces is configured to be connected to a non-processor board card, and the first interface and the second interface are connected to each other via a communication circuit; for the mainboard, a connection-centric design idea is adopted, and the processor board card is regarded to have the same status as the non-processor board card; and because no processor circuit is provided, and only the first interface connected to the processor board card needs to be provided, compared with an original mainboard, an area of the board card in the present application is reduced, and the processor board card and other non-processor board cards may be connected to the mainboard in a stacked manner, thereby reducing the required space, reducing the requirements for the space in the device, and improving the running flexibility of the processor board card simultaneously.

A mainboard includes a plurality of interfaces, a first interface of the plurality of interfaces is configured to be connected to the processor board card having a processor circuit, a second interface of the plurality of interfaces is configured to be connected to a non-processor board card, and the first interface and the second interface are connected to each other via a communication circuit; for the mainboard, a connection-centric design idea is adopted, the processor board card is regarded to have the same status as the non-processor board card; because no processor circuit is provided, and only the first interface connected to the processor board card needs to be provided, compared with an original mainboard, an area of the board card in the present application is reduced, and the processor board card and other non-processor board cards may be connected to the mainboard in a stacked manner.