A system includes a first and a second processing tiles including a first and a second processing elements and on-chip memory (OCMs) respectively. The first and the second OCM are partitioned. A first partition of the first OCM receives and locally stores a first and a second set of data associated with a first operation and a second operations respectively and accessed by the first processing element for processing the first and the second operations. The second OCM receives and locally stores a third set of data associated with a third operation for access by the second processing element for processing the third operation. The first processing tile processes the first operation based on the first set of data as the second processing element is processing the third operation based on the third set of data while a fourth set of data is being received by the first processing tile.

A memory apparatus includes two independent subchannels of double data rate (DDR) memory. Each subchannel includes a number of memory banks, and an input/output (I/O) block having a number of meta data registers. The memory apparatus also includes a processing unit. The processing unit includes an arithmetic logic unit (ALU), an accumulator coupled to an output of the ALU, a controller coupled to the ALU, two multiplexers, each multiplexer coupling one subchannel to an ALU input, and coupling the accumulator to the ALU input, and two multiplexers/demultiplexers. Each multiplexer/demultiplexer is coupled between a memory bank, a corresponding I/O block, one of the two multiplexers, and the accumulator.