Processors, systems and methods are provided for thread level parallel processing. A processor may comprise a plurality of processing elements (PEs) each having a plurality of arithmetic logic units (ALUs) that are configured to execute a same instruction in parallel threads and a plurality of memory ports (MPs) for the plurality of PEs to access a memory unit. Each of the plurality of MPs may comprise an address calculation unit configured to generate respective memory addresses for each thread to access a common area in the memory unit.

An approach for providing low-latency and fast response times required by virtual machine (VM) telecommunication (telco) workloads is disclosed. In one embodiment, a kernel scheduler identifies hypervisor system contexts that are outside of traditional virtual central processing unit (CPU) contexts and servicing telco workloads. The scheduler grants each such context exclusive affinity to a respective physical CPU, up to a configurable maximum number of such grants. The scheduler also increases the CPU reservations in a system resource pool for the hypervisor by one CPU, indicating that there is one fewer physical CPU on which VMs may be placed or moved. The exclusive affinities and CPU reservations may be dynamically adjusted as, e.g., new latency-sensitive VMs are powered on with virtual CPUs that need to be granted exclusive affinity to physical CPUs or contexts no longer relevant to telco workloads are demoted to not have exclusive affinity to physical CPUs.

A method for partitioning executable operations for a reconfigurable computing system includes receiving a set of expressions comprising a plurality of operations and dependencies for those operations, partitioning the plurality of operations into selected executable partitions wherein each selected executable partition conforms to resource constraints for a reconfigurable unit of the reconfigurable computing system. Partitioning the plurality of operations into selected executable partitions may include seeding a candidate partition with an operation, recursively generating an additional candidate partition for each operation adjacent to the candidate partition whose dependent operations are already within the candidate partition or a previously selected partition, and selecting a best candidate partition based on resource cost. A corresponding system and computer-readable medium are also disclosed herein. The system includes a partitioning module that that partitions the plurality of operations into selected executable partitions according to the method describe above.

A processor controls a reconfigurable circuit capable of dynamically reconfiguring a circuit which achieves a task of a computer, the processor executes a process having determining, when reconfiguring each of circuits which achieve a plurality of tasks in the reconfigurable circuit, assigned times of time sharing of the plurality of tasks or priority processing ranks of the plurality of tasks based on costs needed in the reconfigurable circuit for respective circuits which achieve the plurality of tasks.

The present invention provides a system that enhances the experience of using a portable device such as mobile phones, smart phones, Personal Digital Assistants PDA etc. To improve the user experience in the use of a portable device, techniques are used for context characterization, i.e., from a range of conditions possible to detect by the system, such as time (date/time), current location, motion, etc., as well as the historical use of the device, a certain grouping of actions and settings, called context are selected automatically or manually, modifying and setting from that moment the way of user interacts with the device.

A reconfigurable integrated circuit device includes plural processing elements each including an arithmetic circuit, and being configured in any computing state based on the configuration data; and an inter-processing element network which connects the processing elements in any state based on the configuration data. And the processing element inputs an input valid signal and an input data signal, and outputs an output valid signal and an output data signal, and includes an input data holding register, an arithmetic processing circuit, and an output data holding register which holds the computing result data, and when the configuration is updated by configuration data which makes a hold mode valid, regardless of the input valid signal, valid or invalid, the input data holding register holds the input data signal upon the update and the arithmetic processing circuit performs computing processing on the input data signal held in the input data holding register.

A method for partitioning executable operations for a reconfigurable computing system includes receiving a set of expressions comprising a plurality of operations and dependencies for those operations, partitioning the plurality of operations into selected executable partitions wherein each selected executable partition conforms to resource constraints for a reconfigurable unit of the reconfigurable computing system. Partitioning the plurality of operations into selected executable partitions may include seeding a candidate partition with an operation, recursively generating an additional candidate partition for each operation adjacent to the candidate partition whose dependent operations are already within the candidate partition or a previously selected partition, and selecting a best candidate partition based on resource cost. A corresponding system and computer-readable medium are also disclosed herein. The system includes a partitioning module that that partitions the plurality of operations into selected executable partitions according to the method describe above.

A system including an acquisition unit to acquire a first resource information that is information about hardware resources can be used when one or more bit streams related to the first computation node are written to the reconfigurable device. A second resource information is information about hardware resources that can be used when one or more bitstreams related to the second computation node are written to the reconfigurable device. A generation unit generates synthesized resource information that is information about hardware resources that can be used when one or more bit streams based on the first computation node and the second computation node are written to the reconfigurable device, using the first resource information and the second resource information.

A multiple CPU pseudo 3D structure is provided that allows single clock cycle interrupt latency, requires no context storage while taking only a single cycle away from normal programs. Multiple interrupts are given flexible vectored parallel computing responses without timing interactions.