A data processing system includes an array of reconfigurable units and a compiler configured to generate a pipeline of n computational nodes related to a dataflow graph, interleaved between n+1 buffers on the array of reconfigurable units. Each computational node is coupled to perform calculations based on data received from an immediately preceding buffer of the n+1 buffers and store results of the calculations into an immediately following buffer of the n+1 buffers after a latency. The compiler is further configured to remove a buffer of the n+1 buffers from the pipeline based on a comparison of the latencies of the computational nodes. A corresponding method is also disclosed herein.

Techniques for denoising an electromagnetic signal are disclosed. The techniques utilize an antenna, a weight adaptation component, a reservoir computer including a computer interpretable neural network, a delay embedding component, and an output layer computer. The techniques include passively acquiring an electromagnetic signal by the antenna, producing a plurality of reservoir state values by the reservoir computer based on the electromagnetic signal, collecting the plurality of reservoir state values by the delay embedding component into a historical record, determining a plurality of reservoir state value weights by the weight adaptation component based at least in part of the historical record, scaling, by the plurality of reservoir state value weights, to produce a plurality of output values, the plurality of reservoir state values by the output layer computer, and outputting the plurality of output values, where the scaling occurs over a plurality of clock cycles of a clock for the system.

A configurable processing circuit capable of handling multiple threads simultaneously, the circuit comprising a thread data store, a plurality of configurable execution units, a configurable routing network for connecting locations in the thread data store to the execution units, a configuration data store for storing configuration instances that each define a configuration of the routing network and a configuration of one or more of the plurality of execution units, and a pipeline formed from the execution units, the routing network and the thread data store that comprises a plurality of pipeline sections configured such that each thread propagates from one pipeline section to the next at each clock cycle, the circuit being configured to: (i) associate each thread with a configuration instance; and (ii) configure each of the plurality of pipeline sections for each clock cycle to be in accordance with the configuration instance associated with the respective thread that will propagate through that pipeline section during the clock cycle.

Reconfiguring execution pipelines of out-of-order (OOO) computer processors based on phase training and prediction is disclosed. In one aspect, a pipeline reconfiguration circuit is communicatively coupled to an execution pipeline providing multiple selectable pipeline configurations. The pipeline reconfiguration circuit generates a phase identifier (ID) for a phase based on a preceding phase. The phase ID is used as an index into an entry of a pipeline configuration prediction (PCP) table to determine whether training for the phase is ongoing. If so, the pipeline reconfiguration circuit performs multiple training cycles, each employing a pipeline configuration from the selectable pipeline configurations for the execution pipeline, to determine a preferred pipeline configuration for the phase. If training for the phase is complete, the pipeline reconfiguration circuit reconfigures the execution pipeline into the preferred pipeline configuration indicated by the entry before the phase is executed.

A system includes an array of reconfigurable units further including a plurality of configurable elements such as pattern memory units (PMUs), pattern compute units (PCUs), and communication agents. The system further includes a configuration module to provide configuration data to configure the PMUs and PCUs. The systems further includes a compiler configured to generate a pipeline of a plurality of PCUs related to a dataflow graph, interleaved between a plurality of PMUs. Each PCU is coupled to perform calculations based on data received from a preceding PMU and store results of the calculations into a following PMU of the plurality of PMUs after a latency. The compiler is further configured to remove a PMU from the pipeline based on a comparison of the latencies of the PCUs. A corresponding method is also disclosed herein.

A technique to program a compute channel having multiple computational circuit blocks coupled in series in a pipeline can include receiving a machine instruction for the compute channel. The machine instruction is decoded to obtain an opcode, and the opcode can be used as an index to access an opcode entry in an opcode table. The opcode entry contains a pointer to a microoperation, and the pointer can be used to access a microoperation represented by a control entry in a control table and a datapath configuration entry in a datapath table. The microoperation can then be issued to the compute channel by configuring the compute channel with the control entry and the datapath configuration entry.

A method includes: receiving control data at a first data selector of a plurality of data selectors, in which the control data comprises (i) a configuration registry address specifying a location in a configuration state registry and (ii) configuration data specifying a circuit configuration state of a circuit element of a computational circuit; transferring the control data, from the first data selector, to an entry in a trigger table registry; responsive to a first trigger event occurring, transferring the configuration data to the location in the configuration state registry specified by the configuration registry address; and updating a state of the circuit element based on the configuration data.

A first thread is executed in a first pipeline of a first core of an integrated circuit (IC). The first core includes a first set of hardware structures. Response to a command to operate the IC with multiple cores, the first pipeline is flushed. The first core is partitioned to obtain a second core and a third core. The first pipeline is partitioned to obtain a second pipeline and a third pipeline. The first set of hardware structures is partitioned to obtain a second set of hardware structures and a third set of hardware structures. The first thread is executed on the second pipeline of the second core of the IC, the second core including the second set of hardware structures. A second thread is executed on the third pipeline of the third core of the IC, the third core including the third set of hardware structures.

The present invention relates to a configurable logic system (101) programmed to model a logic design for data pipeline between master and slave; and the method of implementation, wherein said system (101) comprises of at least one first register (112) configured to store and transfer at least one data from said master to said slave; wherein said system (101) is configured to operate on one clock and one reset. The system (101) further comprises of at least one first control logic (118) that controls said first register (112) and fourth register (109) to provide hold to the ready signal from the slave to ease timing closure at high speed.

The present invention relates to a configurable logic system (101) programmed to model a logic design for data pipeline between master and slave; and the method of implementation, wherein said system (101) comprises of at least one first register (112) configured to store and transfer at least one data from said master to said slave; wherein said system (101) is configured to operate on one clock and one reset. The system (101) further comprises of at least one first control logic (118) that controls said first register (112) and fourth register (109) to provide hold to the ready signal from the slave to ease timing closure at high speed.