Embodiments of a multiprocessor system are disclosed that may include a plurality of processors interspersed with a plurality of data memory routers, a plurality of bus interface units, a bus control circuit, and a processor interface circuit. The data memory routers may be coupled together to form a primary interconnection network. The bus interface units and the bus control circuit may be coupled together in a daisy-chain fashion to form a secondary interconnection network. Each of the bus interface units may be configured to read or write data or instructions to a respective one of the plurality of data memory routers and a respective processor. The bus control circuit coupled with the processor interface circuit may be configured to function as a bidirectional bridge between the primary and secondary networks. The bus control circuit may also couple to other interface circuits and arbitrate their access to the secondary network.

A reconfigurable edge computing node of a complex system is provided, the edge computing node including a core module executing selectable core software, and selectable input module(s) and/or output module(s) which can be installed in corresponding input/output ports, wherein each of the input module(s) or output module(s) provides a conduit for moving data to or from the complex system, with selections being chosen from catalogs of available input modules, available output modules, and available core software. The edge computing node provides reconfiguration upon attachment of any input or output module(s), or upon installation of any core software, automatically reconfiguring the edge computing node to enable communication between the core module and the input module(s) and output module(s) using compatible protocols. Reconfiguration of the edge computing node has been previously tested for each allowable combination of available selections of the input and output module(s) to satisfy a certification requirement.

A glass circuit assembly employing densely packed components is described. Air cooled computer systems employing densely packed circuit components are described. Relating to agile reconfigurable computer systems a high-resolution substrate having an area of at least 100 cm.sup.2 and selected traces having a line/space dimension of 2 micrometers or less is employed to integrate multiple independently operable clusters of flip chip mounted components in a circuit assembly. Switchable chips and redundant switchable chips may be included on each circuit assembly. Each independently operable cluster of components may include a power distribution chip, a test/monitor chip, and at least one redundant chip for each different logic device and for each different memory device. Chiplet components and combinations may be used to populate independently operable clusters of components. Agile reconfigurable systems are operable to adapt to changing workloads under direction of a system controller.

Methods, systems, and apparatus to reconfigure a computer are disclosed. An example electronic device includes at least one memory, instructions in the electronic device, and processor circuitry to execute instructions to analyze data corresponding to a first configuration of the electronic device to detect a change associated with the electronic device, the first configuration corresponding to a respective first user profile, determine a second configuration of the electronic device based on the detected change, and adjust a configuration of the electronic device from the first configuration to the second configuration.

A reconfigurable data processor comprises an array of configurable units and a bus system configurable to define virtual machines. The system can partition the array of configurable units into a plurality of sets of configurable units, and block communications via the bus system between configurable units within a particular set and configurable units outside the particular set. A memory access controller can be connected to the bus system, configurable to confine access to memory outside the array of configurable units originating from within the particular set to memory space allocated to the particular.

An electronic control device includes: a partially reconfigurable logic circuit in which a calculation unit which is reconfigured and executes calculation and a storage unit which stores calculation target date to be calculated by the calculation unit is configured; and a processing control unit which transmits circuit data for reconfiguring the calculation unit and the calculation target date to the logic circuit. When the processing control unit obtains next calculation target data which is the calculation target date relating to a next calculation unit which is the calculation unit after completion of reconfiguration, transmission of the next calculation target date to the storage unit is started regardless of whether the reconfiguration of the next calculation unit is completed, and upon completion of the reconfiguration, the next calculation unit performs calculation using the next calculation target date.

Representative apparatus, method, and system embodiments are disclosed for configurable computing. A representative system includes an interconnection network; a processor; and a plurality of configurable circuit clusters. Each configurable circuit cluster includes a plurality of configurable circuits arranged in an array; a synchronous network coupled to each configurable circuit of the array; and an asynchronous packet network coupled to each configurable circuit of the array. A representative configurable circuit includes a configurable computation circuit and a configuration memory having a first, instruction memory storing a plurality of data path configuration instructions to configure a data path of the configurable computation circuit; and a second, instruction and instruction index memory storing a plurality of spoke instructions and data path configuration instruction indices for selection of a master synchronous input, a current data path configuration instruction, and a next data path configuration instruction for a next configurable computation circuit.

Representative apparatus, method, and system embodiments are disclosed for configurable computing. A representative system includes an interconnection network; a processor; and a plurality of configurable circuit clusters. Each configurable circuit cluster includes a plurality of configurable circuits arranged in an array; a synchronous network coupled to each configurable circuit of the array; and an asynchronous packet network coupled to each configurable circuit of the array. A representative configurable circuit includes a configurable computation circuit and a configuration memory having a first, instruction memory storing a plurality of data path configuration instructions to configure a data path of the configurable computation circuit; and a second, instruction and instruction index memory storing a plurality of spoke instructions and data path configuration instruction indices for selection of a master synchronous input, a current data path configuration instruction, and a next data path configuration instruction for a next configurable computation circuit.

The present disclosure presents an exemplary tier-based reconfigurable security architecture that can adapt to different use-case scenarios by selecting security tiers and configure parameters in each security tier based on system requirements. An exemplary system comprises a security agent that is configured to monitor system characteristics of embedded components on a system-on-chip and communicate a status of the system characteristics to a reconfigurable service engine integrated on the system-on-chip, such that the reconfigurable service engine is configured to activate one of a plurality of tiers of security based at least upon the status of the system characteristics communicated.

An information processing system backs up an internal state of an arithmetic-device in response to a reception of a message to instruct a backup of the internal state for a number of first paths through which data are input to the arithmetic-device, acquires information of a waiting-time until the arithmetic-device receives the message for the number of first paths, determines whether or not the waiting-time is equal to or more than a first threshold, based on the acquired information, and changes a first configuration that a second arithmetic-device is coupled to a first storage-device through a first arithmetic-device and coupled to a second storage-device through a third arithmetic-device, to a second configuration that the second arithmetic-device is coupled to the first storage-device through the first arithmetic-device, a fourth arithmetic-device, a third storage-device, and a fifth arithmetic-device, when determined that the waiting-time is equal to or more than the first threshold.