A reconfigurable data processor comprises an array of configurable units and a bus system configurable to define virtual machines. The system can partition the array of configurable units into a plurality of sets of configurable units, and block communications via the bus system between configurable units within a particular set and configurable units outside the particular set. A memory access controller can be connected to the bus system, configurable to confine access to memory outside the array of configurable units originating from within the particular set to memory space allocated to the particular.

An architecture disposed in an integrated circuit for in-application programming of flash-based programmable logic devices includes a processor coupled to a processor system bus. An I/O peripheral is coupled to the processor over the system bus and is also coupled to an off-chip data source. A programmable logic device fabric includes flash-based programmable devices. A program controller is coupled to the flash-based programmable devices. An in-application programming controller is coupled to the program controller and is coupled to the processor over the system bus.

An apparatus, and a method therefore, are described, the apparatus according to one embodiment including a security manager and a plurality of clusters of processing elements. Each cluster of the plurality of clusters includes a respective plurality of processing elements. A controller of the apparatus, which may include a security manager, may be configured to control the plurality of clusters to receive a first data stream and a second data stream, control a first plurality of processing elements in a first cluster to process the first data stream using a first security protocol, and control a second plurality of processing elements in a second cluster to process the second data stream using a second security protocol.

Examples described herein provide for an electronic circuit, such as a System-on-Chip (SoC), having a Network-on-Chip (NoC). The NoC is configurable and has capabilities to be partially reconfigured. In an example, a NoC on an integrated circuit is configured. Subsystems on the integrated circuit communicate via the NoC. The NoC is partially reconfigured. A first subset of the NoC is reconfigured during the partial reconfiguration, and a second subset of the NoC is capable of continuing to pass communications uninterruptedly during the partial reconfiguration. After the partial reconfiguration, two or more of the subsystems communicate via the first subset of the NoC.

An electronic control device includes: a partially reconfigurable logic circuit in which a calculation unit which is reconfigured and executes calculation and a storage unit which stores calculation target date to be calculated by the calculation unit is configured; and a processing control unit which transmits circuit data for reconfiguring the calculation unit and the calculation target date to the logic circuit. When the processing control unit obtains next calculation target date which is the calculation target date relating to a next calculation unit which is the calculation unit after completion of reconfiguration, transmission of the next calculation target date to the storage unit is started regardless of whether the reconfiguration of the next calculation unit is completed, and upon completion of the reconfiguration, the next calculation unit performs calculation using the next calculation target date.

Apparatuses, methods, systems, and program products are disclosed for technology management on a hardware component of a device at the time of assembly. An apparatus has a processor and memory storage that stores code executable by the processor. The processor obtains a feature of the hardware component to be removed from the hardware component and operates a virtual fuse that removes a data region associated with the hardware component and permanently removes access to the feature on the hardware component. In response to operating the virtual fuse to remove access to the feature, the processor may indicate the status of the feature on the hardware component.

Disclosed are techniques for external quiesce of a core in a multi-core system. In some aspects, a method for external quiesce of a core in a multi-core system-on-chip (SoC), comprises, at control circuitry for the multi-core SoC, receiving an indication that a core in a multi-core SoC should be quiesced, determining that the core should be externally quiesced, and asserting an external quiesce request input into the core.

A method is disclosed for maintaining a current operating state of an enclosure when a controller card of the enclosure is repaired and/or replaced. In one embodiment, such a method maintains, within a controller card of an enclosure, operating parameters used to establish an operating state of the enclosure. The method further offloads, from the controller card while the controller card is installed in the enclosure, the operating parameters to a location external to the controller card. Upon removal of the controller card from the enclosure, the method maintains the operating state of the enclosure using the operating parameters stored in the external location. Upon reinstalling the controller card in the enclosure, the method optionally retrieves the operating parameters from the external location and initializes the controller card with the operating parameters. A corresponding system and computer program product are also disclosed.

Embodiments herein describe a SoC that includes a programmable NoC that can be reconfigured to support different interface communication protocols. In one embodiment, the NoC includes ingress and egress logic blocks which permit hardware elements in the SoC (e.g., processors, memory, programmable logic blocks, etc.) to transmit and receive data using the NoC. The ingress and egress logic blocks may first be configured to support a particular communication protocol for interfacing with the hardware elements. However, at a later time, the user may wish to reconfigure the ingress and egress logic blocks to support a different communication protocol. In response, the SoC can reconfigure the NoC such that the ingress and egress logic blocks support the new communication protocol used by the hardware elements. In this manner, the programmable NoC can support multiple communication protocols used to interface with other hardware elements in the SoC.

In an approach to optimizing dynamic system reconfiguration, a computer receives an active system configuration and a target system configuration from a system administrator, where the target system configuration includes two or more logical partitions. A computer determines one or more reconfiguration actions required to transform the active system configuration to the target system configuration. A computer generates a dependency graph based on the determined reconfiguration actions. A computer divides the dependency graph along the two or more logical partitions. A computer sorts the determined reconfiguration actions by associated dependencies. A computer orders the determined reconfiguration actions based on a priority of each of the two or more logical partitions. A computer runs a first simulation of the determined reconfiguration actions for each of the two or more logical partitions. A computer performs the determined reconfiguration actions for each of the two or more logical partitions.