Embodiments herein describe a distributed configuration system for a configurable device. Instead of relying solely on a central configuration manager to distribute configuration information to various subsystems in the device, the embodiments herein include configuration interface managers (CIM) that are distributed in different regions of the device, whether those regions are in one integrated circuit or include multiple integrated circuits. The embodiments can still use a central configuration manager to distribute configuration information in a device image to the plurality of CIMs, which can then forward the configuration information to their assigned regions.

A data processing apparatus is provided. The data processing apparatus includes hardware locating circuitry for locating hardware associated with processing circuitry, and for causing hardware configuration data relating to the hardware to be generated. Providing circuitry causes the hardware configuration data to be provided to an operating system executing on the processing circuitry to enable the operating system to utilise the hardware.

A graphics processing pipeline includes a rasteriser, an early culling tester, a renderer, a late culling tester, and a culling test data buffer that stores data values for use by the early and late culling testers. The testing of fragments by the early and late culling testers is controlled in accordance with a first set of state information indicative of when a culling test operation to be used to determine whether to cull the fragments is to be performed, and a second set of state information indicative of when to determine whether to update the culling test data buffer with data for the fragments based on a culling test operation, allocated to the fragments.

Disclosed are techniques for external quiesce of a core in a multi-core system. In some aspects, a method for external quiesce of a core in a multi-core system-on-chip (SoC), comprises, at control circuitry for the multi-core SoC, receiving an indication that a core in a multi-core SoC should be quiesced, determining that the core should be externally quiesced, and asserting an external quiesce request input into the core.

One embodiment provides a method, including: identifying, based on context data, a location of an information handling device; accessing a settings profile for the information handling device that is based on the identified location; determining, using a processor, whether at least one current setting on the information handling device is inconsistent with the settings profile; and adjusting, responsive to determining that the at least one current setting is inconsistent with the settings profile, the at least one current setting to match the settings profile for the location. Other aspects are described and claimed.

Embodiments of a multiprocessor system are disclosed that may include a plurality of processors interspersed with a plurality of data memory routers, a plurality of bus interface units, a bus control circuit, and a processor interface circuit. The data memory routers may be coupled together to form a primary interconnection network. The bus interface units and the bus control circuit may be coupled together in a daisy-chain fashion to form a secondary interconnection network. Each of the bus interface units may be configured to read or write data or instructions to a respective one of the plurality of data memory routers and a respective processor. The bus control circuit coupled with the processor interface circuit may be configured to function as a bidirectional bridge between the primary and secondary networks. The bus control circuit may also couple to other interface circuits and arbitrate their access to the secondary network.

An architecture disposed in an integrated circuit for in-application programming of flash-based programmable logic devices includes a processor coupled to a processor system bus. An I/O peripheral is coupled to the processor over the system bus and is also coupled to an off-chip data source. A programmable logic device fabric includes flash-based programmable devices. A program controller is coupled to the flash-based programmable devices. An in-application programming controller is coupled to the program controller and is coupled to the processor over the system bus.

Embodiments of a multiprocessor system are disclosed that may include a plurality of processors interspersed with a plurality of data memory routers, a plurality of bus interface units, a bus control circuit, and a processor interface circuit. The data memory routers may be coupled together to form a primary interconnection network. The bus interface units and the bus control circuit may be coupled together in a daisy-chain fashion to form a secondary interconnection network. Each of the bus interface units may be configured to read or write data or instructions to a respective one of the plurality of data memory routers and a respective processor. The bus control circuit coupled with the processor interface circuit may be configured to function as a bidirectional bridge between the primary and secondary networks. The bus control circuit may also couple to other interface circuits and arbitrate their access to the secondary network.

A reconfigurable processor chip includes: a plurality of reconfigurable processing elements based on distributed storage, components of the reconfigurable processing elements being logically interconnected. The components include: a reconfigurable computing component configured to calculate data; a data flow controller using a data flow driving mode, the data flow driving mode is configured to control start and end of a computing task and a data transmission task based on data flow information about the computing task and message transferring of upstream and downstream reconfigurable processing elements; a distributed memory configured to implement data storage of a corresponding reconfigurable processing element; and a programmable data routing element configured to implement communication between the plurality of reconfigurable processing elements to control a direction of a data packet, and implement flexible transmission of the data packet.

A technique to program a compute channel having multiple computational circuit blocks coupled in series in a pipeline can include receiving a machine instruction for the compute channel. The machine instruction is decoded to obtain an opcode, and the opcode can be used as an index to access an opcode entry in an opcode table. The opcode entry contains a pointer to a microoperation, and the pointer can be used to access a microoperation represented by a control entry in a control table and a datapath configuration entry in a datapath table. The microoperation can then be issued to the compute channel by configuring the compute channel with the control entry and the datapath configuration entry.