A reconfigurable data processor comprises an array of configurable units including a plurality of tiles and a bus system. The bus system includes boundary switches on tile boundaries, configurable to partition the array into sets of configurable units spanning one or more tiles. A configuration controller is configured to load a configuration file to form a virtual machine across multiple tiles by setting the boundary switches to isolate the virtual machine.

A system includes plurality of processor cores and a memory device storing executable code that, when executed by the plurality of processor cores, causes the plurality of processor cores to: receive a specification for including a request for a first number of processor cores and a limit of a second number of processor cores that is greater than the first number; reserve a full set of processor cores including the second number of processor cores for use by an instance of the software module; instantiate an instance of a software module; and configure the instance to use a reduced set of processors cores, the reduced set of processor cores including a third number of processor cores that is greater than the first number and less than the second number.