The invention relates to a device for the label-free quantitative spectroscopic determination of the binding kinetics of an analyte. Essential components of the device, namely a light source (2), optical elements (5; 6; 7; 8; 9; 13; 13′) for beam guidance and for optically influencing the light of the light source (2) and light modes emitted by a microsensor (functionalized spherical microparticle) retained in a microstructure (3) as a result of the exposure to the light of the light source (2), a spectrometer, which consists of an optical receiver (10) for the emitted light modes and an evaluation unit, actuators (14; 15) for positioning a carrier (4) with the microstructure (3) arranged thereon, and at least one control unit, are jointly arranged in an apparatus (1) having an apparatus housing (11). The light, namely the light of the light source (2) and the light modes emitted by a microparticle in question as a result of the exposure to said light, is guided in three different planes within the apparatus housing (11) by means of the optical elements (5; 6; 7; 8; 9; 13; 13), in particular by means of a first optical deflecting element (6) and by means of a second optical deflecting element (7).

A dataflow graph for an application has operation units that are configured to be producers and consumers of tensors. A write access pattern of a particular producer specifies an order in which the particular producer generates elements of a tensor, and a read access pattern of a corresponding consumer specifies an order in which the corresponding consumer processes the elements of the tensor. The technology disclosed detects conflicts between the producers and the corresponding consumers that have mismatches between the write access patterns and the read access patterns. A conflict occurs when the order in which the particular producer generates the elements of the tensor is different from the order in which the corresponding consumer processes the elements of the tensor. The technology disclosed resolves the conflicts by inserting buffers between the producers and the corresponding consumers.

A data processing apparatus is configured to solve a specific problem using a simple hardware. The data processing apparatus comprises a state data processing unit configured to iterate update of state data by a predetermined time evolutional process, a cost evaluation unit configured to evaluate a cost function for current state data, and an error calculation unit configured to calculate error values relating to amplitude homogeneity of the current state data, wherein the state data processing unit performs the time evolutional process on the state data to update the current state data based on the cost function and the error values which are calculated by the error calculation unit.

Methods are provided for configuring a reconfigurable hardware device to execute a user application. Such a method includes providing static shell logic on the device. The static shell logic is controlled by a primary management core for managing operation of the device, and has a predetermined hardware interface. The method includes configuring on the device, via the primary management core, dynamic shell logic for implementing dynamically-selected shell functionality. The dynamic shell logic includes a secondary management core, adapted to communicate with the primary management core via the hardware interface, for managing operation of the dynamic shell logic. The method further comprises configuring on the device, via the primary management core, application logic, having an interface with the dynamic shell logic, for executing the user application. The secondary management core uploads to the primary management core dynamic code to adapt the primary management core for use with the dynamic shell logic.

The technology disclosed relates to allocating available physical compute units (PCUs) and/or physical memory units (PMUs) of a reconfigurable data processor to operation units of an operation unit graph for execution thereof. In particular, it relates to selecting, for evaluation, an intermediate stage compute processing time between lower and upper search bounds of a generic stage compute processing time, determining a pipeline number of the PCUs and/or the PMUs required to process the operation unit graph, and iteratively, initializing new lower and upper search bounds of the generic stage compute processing time and selecting, for evaluation in a next iteration, a new intermediate stage compute processing time taking into account whether the pipeline number of the PCUs and/or the PMUs produced for a prior intermediate stage compute processing time in a previous iteration is lower or higher than the available PCUs and/or PMUs.

A method of processing partitions of a tensor in a target order includes receiving, by a reorder unit and from two or more producer units, a plurality of partitions of a tensor in a first order that is different from the target order, storing the plurality of partitions in the reorder unit, and providing, from the reorder unit, the plurality of partitions in the target order to one or more consumer units. In an example, the one or more consumer units process the plurality of partitions in the target order.

Methods, systems, and computer programs are presented for processing Ethernet packets at a Field Programmable Gate Array (FPGA). One programmable integrated circuit includes: an internal network on chip (iNOC) comprising rows and columns; clusters, coupled to the iNOC, comprising a network access point (NAP) and programmable logic; and an Ethernet controller coupled to the iNOC. When the controller operates in packet mode, each complete inbound Ethernet packet is sent from the controller to one of the NAPs via the iNOC, where two or more NAPs are configurable to receive the complete inbound Ethernet packets from the controller. The controller is configurable to operate in quad segment interface (QSI) mode where each complete inbound Ethernet packet is broken into segments, which are sent from the controller to different NAPs via the iNOC, where two or more NAPs are configurable to receive the complete inbound Ethernet packets from the controller.

The technology disclosed relates to allocating available physical compute units (PCUs) and/or physical memory units (PMUs) of a reconfigurable data processor to operation units of an operation unit graph for execution thereof. In particular, it relates to selecting, for evaluation, an intermediate stage compute processing time between lower and upper search bounds of a generic stage compute processing time, determining a pipeline number of the PCUs and/or the PMUs required to process the operation unit graph, and iteratively, initializing new lower and upper search bounds of the generic stage compute processing time and selecting, for evaluation in a next iteration, a new intermediate stage compute processing time taking into account whether the pipeline number of the PCUs and/or the PMUs produced for a prior intermediate stage compute processing time in a previous iteration is lower or higher than the available PCUs and/or PMUs.

A dataflow graph for an application has operation units that are configured to be producers and consumers of tensors. A write access pattern of a particular producer specifies an order in which the particular producer generates elements of a tensor, and a read access pattern of a corresponding consumer specifies an order in which the corresponding consumer processes the elements of the tensor. The technology disclosed detects conflicts between the producers and the corresponding consumers that have mismatches between the write access patterns and the read access patterns. A conflict occurs when the order in which the particular producer generates the elements of the tensor is different from the order in which the corresponding consumer processes the elements of the tensor. The technology disclosed resolves the conflicts by inserting buffers between the producers and the corresponding consumers.

The present disclosure is directed to 3-D stacked architecture for Programmable Fabrics and Central Processing Units (CPUs). The 3-D stacked orientation enables reconfigurability of the fabric, and allows the fabric to function using coarse-grained and fine-grained acceleration for offloading CPU processing. Additionally, the programmable fabric may be able to function to interface with multiple other compute chiplet components in the 3-D stacked orientation. This enables multiple compute components to communicate without the need for offloading the data communications between the compute chiplets.