Systems and methods are disclosed for to generation of dynamic design flows for integrated circuits. For example, a method may include accessing a design flow configuration data structure, wherein the design flow configuration data structure is encoded in a tool control language; based on the design flow configuration data structure, selecting multiple flowmodules from a set of flowmodules, wherein each flowmodule provides an application programming interface, in the tool control language, to a respective electronic design automation tool; based on the design flow configuration data structure, generating a design flow as a directed acyclic graph including the selected flowmodules as vertices; and generating an output integrated circuit design data structure, based on one or more input integrated circuit design data structures, using the design flow to control the respective electronic design automation tools of the selected flowmodules.

A method and a system are disclosed for solving a mixed-integer programming problem, the method comprising obtaining an indication of a mixed-integer programming optimization problem; until a performance criterion is met: providing the mixed-integer programming optimization problem to an optimization oracle adapted for solving the mixed-integer programming optimization problem using a feasibility pump technique and comprising an optimization solver, initializing parameters of an optimization oracle and an initial solution pair, the parameters comprising Monte-Carlo simulation parameters, a list of neighborhood functions and a measure of fractionality, and performing iterative calls to the optimization solver until a stopping condition is met; and providing at least one corresponding solution obtained from the optimization solver.

A method and a system are disclosed for solving a mixed-integer programming problem, the method comprising obtaining an indication of a mixed-integer programming optimization problem; until a performance criterion is met: providing the mixed-integer programming optimization problem to an optimization oracle adapted for solving the mixed-integer programming optimization problem using a feasibility pump technique and comprising an optimization solver, initializing parameters of an optimization oracle and an initial solution pair, the parameters comprising Monte-Carlo simulation parameters, a list of neighborhood functions and a measure of fractionality, and performing iterative calls to the optimization solver until a stopping condition is met; and providing at least one corresponding solution obtained from the optimization solver.

An integrated circuit includes logic circuits, a logic analyzer circuit, and a multiplexer circuit configurable to provide a value of a signal selected from one of the logic circuits to the logic analyzer circuit. The logic analyzer circuit is configured to store the value of the signal selected by the multiplexer circuit. A method is provided for capturing signals within an integrated circuit. The method includes providing a first logic signal from a first logic circuit to a multiplexer circuit, providing a second logic signal from a second logic circuit to the multiplexer circuit, selecting one of the first logic signal or the second logic signal as a selected signal using the multiplexer circuit, and storing a value of the selected signal in the logic analyzer circuit in the integrated circuit.

Described are navigational systems for vehicles including modular, field-swappable and field-configurable components and a plurality of operational modes.

Described are navigational systems for vehicles including modular, field-swappable and field-configurable components and a plurality of operational modes.

A method includes instantiating a simulation of an electronic design for a device under test (DUT) in hardware design language responsive to a user selection thereof. A subset of leaf nodes from a plurality of leaf nodes from the electronic design with input/output signaling of more than two values is identified. A hierarchical path for each leaf node of the plurality of leaf nodes of the electronic design for the DUT with respect to a testbench is calculated. A bypass module for the subset of leaf nodes is generated. The bypass module is generated in response to detecting presence of the subset of leaf nodes in the electronic design with input/output signaling of more than two values. The bypass module facilitates communication between the testbench and the subset of leaf nodes. Leaf nodes other than the subset of leaf nodes communicate with the testbench without communicating through the bypass module.

A debug system for debugging a logic design includes an adaptor and a debug station connected to the adaptor. The logic design includes a plurality of design modules. The adaptor is configured to receive an emulation output of the logic design. The emulation output includes a design snapshot of the logic design and input signals to the logic design that both are recorded during an emulation process of the logic design. The debug station is configured to generate, based on the emulation output and a netlist of a design module of the logic design, an emulation history of the design module.

An efficient and cost-effective method for usage of emulation machine is disclosed, in which a new concept and use model called debug station is described. The debug station methodology lets people run emulation using a machine from one vendor, and debug designs using a machine from another vendor, so long as these machines meet certain criteria. The methodology and its associated hardware hence are called a ‘platform neutral debug station.’ The debug station methodology breaks loose usage of emulation machines, where people can choose the best machine for running a design, and the best machine for debugging, and they do not need to be the same. Unlike the past, where people needed to run emulation and debug a design using same emulator from beginning to the end, the mix-and-match method described herein allows users to use emulators in the most efficient way, and often most cost effective too.

A system includes a first cross-point switch receiving a first plurality of clock inputs and outputting a first plurality of clock outputs, a first plurality of buffering devices receiving the first plurality of clock outputs and outputting a first plurality of buffered clock signals synchronized with each other, a first plurality of connectors receiving the first plurality of buffered clock signals and outputting a plurality of blade signals to a plurality of blades. Each blade includes a plurality of programmable logic devices, an operation of which is synchronized based on the first plurality of clock inputs. Each blade includes a second cross-point switch to receive a blade signal of the plurality of blade signals. The second cross-point switch outputs a second plurality of clock outputs based on the received blade signal, and the second plurality of clock outputs are provided to the programmable logic devices.