The present invention discloses a method for viewing simulation signals of digital products and a simulation system, the method includes: when performing FPGA simulation on digital products, reading out all external port status data of digital products in real time and recording, meanwhile reading out all internal status data of digital products once every interval time and recording; after completing the simulation, when needing a back trace to check the data of digital products in a certain clock cycle, reading out the internal status data of digital products stored at the last time point before this clock cycle and the external port status data at said time point in the recorded simulation data; and taking the read-out data as an initial status data of the FPGA, then reading out all internal status data of digital products clock by clock until running to the clock cycle that needs to be viewed.

Using a flat shell for an accelerator card includes reading a flat shell from one or more computer readable storage media using computer hardware, wherein the flat shell is a synthesized, unplaced, and unrouted top-level circuit design specifying platform circuitry. A kernel specifying user circuitry is synthesized using the computer hardware. The kernel is obtained from the one or more computer readable storage media. The synthesized kernel is linked, using the computer hardware, to the flat shell forming a unified circuit design. The unified circuit design is placed and routed, using the computer hardware, to generate a placed and routed circuit design specifying the platform circuitry and the user circuitry for implementation in an integrated circuit.

A system and method transforms a model of electronic circuit to improve simulation speed and/or reduce emulation area. The model may include storage elements; one or more of these storage elements may be represented by dense memory, and the storage elements may be represented by references thereto.

One embodiment illustrated herein includes a hardware system for simulating a network physical layer for communication channels. The hardware system includes a plurality of hardware processors configurable to model a network physical layer and communication channels. The hardware processors include an opcode processing unit. The hardware processors further include a programmable state machine coupled to the opcode processing unit. The programmable state machine is configured to be programmed by the opcode processing unit using a low-level hardware programming language comprising opcodes having waveform processing specific semantics so as to configure the state machine for specific waveforms or specific network physical layer characteristics.

A hardware system for simulating a network physical layer for communication channels. The hardware system includes a plurality of hardware processors configurable to model a network physical layer and communication channels. The hardware system is further implemented where the hardware processors are configured such that a single set of hardware, including a single set of gates and registers, is used in a single simulation to model a plurality of virtual routers for different nodes.

A method for creating an allocation map, wherein the allocation map is created based on an FPGA source code, wherein the source code uses at least a first signal at a first location, wherein at least a first register is mapped to the first signal, wherein in the allocation map, the first signal and the first register are listed as mapped to one another, wherein a second signal is used at a second location in the FPGA source code, wherein it is automatically detected that the value of the second signal can be determined from the value of the first signal according to a first calculation rule, wherein in the allocation map, the second signal, the first register and the first calculation rule are listed as mapped to one another.

A method for creating an allocation map, wherein the allocation map is created based on an FPGA source code, wherein the source code uses at least a first signal at a first location, wherein at least a first register is mapped to the first signal, wherein in the allocation map, the first signal and the first register are listed as mapped to one another, wherein a second signal is used at a second location in the FPGA source code, wherein it is automatically detected that the value of the second signal can be determined from the value of the first signal according to a first calculation rule, wherein in the allocation map, the second signal, the first register and the first calculation rule are listed as mapped to one another.

A method of operation of a computing system includes: providing a first cluster having a first kernel unit for managing a first reconfigurable hardware device; analyzing an application descriptor associated with an application; generating a first bitstream based on the application descriptor for loading the first reconfigurable hardware device, the first bitstream for implementing at least a first portion of the application; and implementing a first fragment with the first bitstream in the first cluster.

A method of operation of a computing system includes: providing a first cluster having a first kernel unit for managing a first reconfigurable hardware device; analyzing an application descriptor associated with an application; generating a first bitstream based on the application descriptor for loading the first reconfigurable hardware device, the first bitstream for implementing at least a first portion of the application; and implementing a first fragment with the first bitstream in the first cluster.

Systems, devices, and methods related to a Deep Learning Accelerator and memory are described. For example, an integrated sensor device may be configured to execute instructions with matrix operands and configured with: a sensor to generate measurements of stimuli; random access memory to store instructions executable by the Deep Learning Accelerator and store matrices of an Artificial Neural Network; a host interface connectable to a host system; and a controller to store the measurements generated by the sensor into the random access memory as an input to the Artificial Neural Network. After the Deep Learning Accelerator generates in the random access memory an output of the Artificial Neural Network by executing the instructions to process the input, the controller may communicate the output to a host system through the host interface.