An implementation-quality synthesis process begins with a logical design of an integrated circuit and, through a series of steps, generates a fully synthesized physical design of the integrated circuit. One of the steps is clock synthesis, which generates the clock network for the integrated circuit. In certain embodiments, a method includes the following steps. A reduced clock synthesis process is applied, rather than the implementation-quality clock synthesis process. This generates a clock network for the logical design, which will be referred to as a proxy clock network because it is used as a proxy to estimate power consumption of the fully synthesized clock network. Because the reduced clock synthesis process runs much faster than the implementation-quality clock synthesis process, the front end designer may use these power estimates in the front end design process, including to explore different design variations in the logical design.

An implementation-quality synthesis process begins with a logical design of an integrated circuit and, through a series of steps, generates a fully synthesized physical design of the integrated circuit. One of the steps is clock synthesis, which generates the clock network for the integrated circuit. In certain embodiments, a method includes the following steps. A reduced clock synthesis process is applied, rather than the implementation-quality clock synthesis process. This generates a clock network for the logical design, which will be referred to as a proxy clock network because it is used as a proxy to estimate power consumption of the fully synthesized clock network. Because the reduced clock synthesis process runs much faster than the implementation-quality clock synthesis process, the front end designer may use these power estimates in the front end design process, including to explore different design variations in the logical design.

Techniques and systems for determining an output waveform at an output of a complementary metal-oxide-semiconductor (CMOS) logic gate are described. Some embodiments can identify at least one set of inputs of the CMOS logic gate that, when switched together, causes multiple transistors coupled in parallel to simultaneously turn-on and drive the output of the CMOS logic gate. Next, the embodiments can determine a set of current source models that are coupled in parallel to model the CMOS logic gate when the set of inputs of the CMOS logic gate are switched together. The embodiments can then simulate the set of current source models together to determine the output waveform at the output of the CMOS logic gate when the set of inputs of the CMOS logic gate are switched together.

Techniques and systems for determining an output waveform at an output of a complementary metal-oxide-semiconductor (CMOS) logic gate are described. Some embodiments can identify at least one set of inputs of the CMOS logic gate that, when switched together, causes multiple transistors coupled in parallel to simultaneously turn-on and drive the output of the CMOS logic gate. Next, the embodiments can determine a set of current source models that are coupled in parallel to model the CMOS logic gate when the set of inputs of the CMOS logic gate are switched together. The embodiments can then simulate the set of current source models together to determine the output waveform at the output of the CMOS logic gate when the set of inputs of the CMOS logic gate are switched together.

A method includes acquiring a vector data signal associated with a circuit design, performing a timing update to determine timing information for the circuit design, and identifying a glitch in the circuit design based on a shifted vector waveform. The timing information includes a signal delay associated with a cell of the circuit design. The shifted vector waveform is generated by shifting the vector data signal based on the timing information.

This disclosure relates to signal observability rating. In an example, a method can include propagating a clock signal through a respective module of a circuit design in a forward and backward direction, evaluating clock signal propagation results for the respective module based on a forward and backward clock signal propagation of the clock signal to compute an observability rating for a data signal to be processed by the respective module during formal verification, and updating a current observability rating of the respective property for the data signal to the computed observability rating.

This disclosure relates to signal observability rating. In an example, a method can include propagating a clock signal through a respective module of a circuit design in a forward and backward direction, evaluating clock signal propagation results for the respective module based on a forward and backward clock signal propagation of the clock signal to compute an observability rating for a data signal to be processed by the respective module during formal verification, and updating a current observability rating of the respective property for the data signal to the computed observability rating.

To increase the efficiency of electronic design automation, at an end point of physical design synthesis optimization flow for a putative integrated circuit design having a plurality of nets, identify at least one congested region in the putative integrated circuit design. Identify those of the nets of the putative integrated circuit design traversing through the at least one congested region, to obtain a plurality of candidate nets for demotion. Demote a plurality of selected nets, selected from the plurality of candidate nets for demotion, from an upper routing layer of the putative integrated circuit design to a lower routing layer of the putative integrated circuit design. At least some of the plurality of selected nets experience a loss of timing quality of result after the demoting.

To increase the efficiency of electronic design automation, at an end point of physical design synthesis optimization flow for a putative integrated circuit design having a plurality of nets, identify at least one congested region in the putative integrated circuit design. Identify those of the nets of the putative integrated circuit design traversing through the at least one congested region, to obtain a plurality of candidate nets for demotion. Demote a plurality of selected nets, selected from the plurality of candidate nets for demotion, from an upper routing layer of the putative integrated circuit design to a lower routing layer of the putative integrated circuit design. At least some of the plurality of selected nets experience a loss of timing quality of result after the demoting.

A method for providing an integrated circuit design is disclosed. The method includes receiving and synthesizing a behavioral description of an integrated circuit design. The method includes generating, based on the synthesized behavioral description, a layout by placing and routing a plurality of transistor-based cells. The method includes selectively accessing a cell library that includes a plurality of non-transistor-based cells, each of the plurality of non-transistor-based cells associated with a respective delay value. The method includes updating the layout by inserting one or more of the plurality of non-transistor-based cells.