The present disclosure discloses a driving method, a driving circuit, and a display device. The driving method includes: acquiring driving data that includes N-bit data; dividing the N-bit data into M groups of sub-bit data in sequence, wherein each group of the sub-bit data includes (N/M)-bit data, M is a positive divisor of N, and M is not 1 or N; and driving, by adopting a corresponding driving voltage and corresponding driving time, a corresponding light-emitting unit to emit light, according to each group of the sub-bit data.

A display driver for driving a display device including a pixel array is provided. The display driver includes a plurality of driving channels. The driving channels is configured to output driving signals in a pulse width modulation manner to drive the pixel array to illuminate in a first frame period which is being divided into a plurality of subframe periods. A first driving channel of the plurality of driving channels outputs a first driving signal in a first subframe period combination. A second driving channel of the plurality of driving channels outputs a second driving signal in a second subframe period combination different than the first subframe period combination. Each of the first subframe period combination and the second subframe period combination comprises at least one subframe period of the first frame period.

Systems and methods for improving operating characteristics of displays such as liquid crystal on silicon displays.

A projector includes a DMD that forms an image, a projection lens that projects the image formed by the DMD on a projected surface, and a display control unit that controls an image forming operation of the DMD. The display control unit forms a frame image by sequentially forming a plurality of images using a combined pixel which is configured of a plurality of pixels, and with respect to temporally continuous two images, the display control unit forms one image at a position that is shifted by a distance that corresponds to the pixel pitch of the DMD in a predetermined direction relative to the other image.

A control method is provided for suppressing a flicker phenomenon even if frame periods vary in length. The control method controls an emission period and an extinction period of a frame period, which is a period in which one image continues to be displayed. When a signal indicating start of a frame period is detected, as the frame period, n subframe periods that configure the frame period, where n is an integer greater than or equal to 2, are sequentially started from the first subframe period, after a predetermined period of time has elapsed since the detection of the signal. All of the n subframe periods are controlled to have a substantially same length determined in advance and to have a substantially same ratio between the emission period and the extinction period, determined in advance, the ratio being referred to as a duty ratio.

The present disclosure relates to a driving method for a display device and a display device. The display device includes a display driver, the display driver includes a plurality of driving channels each of which drives corresponding display unit according to display data in a pulse width modulation manner within one frame period, the method comprises: selectively enabling, in each sub-frame subset among a plurality of different sub-frame subsets of the frame period, different channel subset among a plurality of channel subsets of the plurality of driving channels to drive corresponding display unit, wherein each channel subset of the plurality of channel subsets includes two or more driving channels among the plurality of driving channels.

An image processing device includes a correction section adapted to perform a correction process of data of low (N−M) bits (N and M are integers fulfilling N>M) of a gray level value represented by input video data in a case in which the data of the low (N−M) bits coincides with a predetermined bit sequence, and a modulation section adapted to set data on which the correction process has been performed as target data with respect to the pixel having the data of the low (N−M) bits coinciding with the predetermined bit sequence, and perform a modulation process of modulating at least a part of data of high M bits of the target data using a bit sequence defined in accordance with the data of the low (N−M) bits in a plurality of unit periods.

A circuit device includes a scan line drive circuit that drives a plurality of scan lines of an electro-optical element. A field for constituting one image includes a plurality of subfields. The scan line drive circuit selects once a scan line group to be selected among the plurality of scan lines, in a subfield included in the plurality of subfields. The scan line group includes a scan line connected to a pixel circuit to which an i-th bit is written in a subfield, and a scan line connected to a pixel circuit to which a j-th bit is written in a subfield.

An LED display system has and LED display panel coupled to a driver circuitry. The driver circuitry includes a scrambled PWM generator, a register, and a memory. The scrambled PWM generator receives an image data from an external source and, after certain compensations, is sent to a scramble PWM generator to be distributed according to a new set of rules that involves a compensation image data K. Image data K can be an empirical value or obtained according a formula using coefficients p and q, which can be obtained by calibration.

The present disclosure provides a signal generation apparatus, a driving chip, a display system an LED displaying driving method. A circuit comprises a first generation device for generating a first PWM wave with period T1; a second generation device for generating a delayed clock signal with period T2, T1=NT2, the first time is delayed by F×T2 compared with the second time, the first time is the time corresponding to a first rising edge of the delayed clock signal, the second time is the time corresponding to a first rising edge of the first PWM wave; a third generation device for generating a third PWM wave with period T3 according to the first PWM wave the delayed clock signal, T3=T1+F×T2, a first rising edge of the third PWM wave is synchronous with the first rising edge of the first PWM wave.