A display device includes: a substrate including at least two layers; a driving circuit on the substrate; a pixel electrode connected to the driving circuit; a common electrode on the pixel electrode; a display layer between the pixel electrode and the common electrode; and a thermoelectric element located between the at least two layers of the substrate.

A display device includes: a substrate including at least two layers; a driving circuit on the substrate; a pixel electrode connected to the driving circuit; a common electrode on the pixel electrode; a display layer between the pixel electrode and the common electrode; and a thermoelectric element located between the at least two layers of the substrate.

Methods for driving an electro-optic displays having a plurality of display pixels are described. The method includes determining a level of stress quantity for a display pixel of the electro-optic display based on at least one prior update to the optical state of the display pixel, and receiving a request to update the optical state of the display pixel. The method also includes applying driving waveforms from first or second update schemes to the display pixel depending on the update scheme used for an immediately prior update of the display pixel and comparisons of the level of stress quantity to two level of stress thresholds.

Methods for driving an electro-optic displays having a plurality of display pixels are described. The method includes determining a level of stress quantity for a display pixel of the electro-optic display based on at least one prior update to the optical state of the display pixel, and receiving a request to update the optical state of the display pixel. The method also includes applying driving waveforms from first or second update schemes to the display pixel depending on the update scheme used for an immediately prior update of the display pixel and comparisons of the level of stress quantity to two level of stress thresholds.

A gate driver includes a stage configured to output a gate signal, the stage including an input part configured to control a voltage of a first node and a voltage of a second node based on signals supplied to a first input terminal and a second input terminal, an output part configured to supply a voltage of a first power source or a voltage of a second power source as the gate signal to an output terminal based on a voltage of a third node and a voltage of a fourth node, a first signal processing part configured to supply the voltage of the second power source to the fourth node based on the voltage of the first node, or to electrically connect the second node and the fourth node through a fifth node based on a signal supplied to a third input terminal, and a second signal processing part including a first transistor connected between the third node and a sixth node to control the voltage of the third node based on an operation of the first transistor.

A display controller disposed in a display device that includes a flash memory and an integrated circuit is provided. The flash memory stores display device information of the display device. The integrated circuit includes a first and a second power conversion circuit and an accessing circuit. The first power conversion circuit converts an external power received from an external power adapter to a power in a first power domain. The second power conversion circuit converts a host power received from a host to the power of a second power domain and outputs the power to a flash memory such that the flash memory operates accordingly. The accessing circuit operates according to the power of the second power domain to access and transmit the display device information from the flash memory to the host when the first power conversion circuit is not in operation.

A display controller disposed in a display device that includes a flash memory and an integrated circuit is provided. The flash memory stores display device information of the display device. The integrated circuit includes a first and a second power conversion circuit and an accessing circuit. The first power conversion circuit converts an external power received from an external power adapter to a power in a first power domain. The second power conversion circuit converts a host power received from a host to the power of a second power domain and outputs the power to a flash memory such that the flash memory operates accordingly. The accessing circuit operates according to the power of the second power domain to access and transmit the display device information from the flash memory to the host when the first power conversion circuit is not in operation.

Embodiments of the present disclosure provide a shift register unit, a gate driving circuit and driving method thereof, and a display apparatus. The shift register unit comprises a first controlling sub-circuit, a second controlling sub-circuit, a first pulling up sub-circuit, a second pulling up sub-circuit, a first pulling down sub-circuit and a second pulling down sub-circuit. The first controlling sub-circuit controls the potential at the first node. The voltage of a second clock signal terminal can be outputted to the first and the second outputting terminals by the first and the second pulling down sub-circuits, respectively. The first node, the first clock signal terminal and the second voltage terminal may control the potential at a second node through the second controlling sub-circuit. Under the control of the potential at the second node, the voltage of the second voltage terminal can be outputted to the first and the second outputting terminals.

Embodiments of the present disclosure provide a shift register unit, a gate driving circuit and driving method thereof, and a display apparatus. The shift register unit comprises a first controlling sub-circuit, a second controlling sub-circuit, a first pulling up sub-circuit, a second pulling up sub-circuit, a first pulling down sub-circuit and a second pulling down sub-circuit. The first controlling sub-circuit controls the potential at the first node. The voltage of a second clock signal terminal can be outputted to the first and the second outputting terminals by the first and the second pulling down sub-circuits, respectively. The first node, the first clock signal terminal and the second voltage terminal may control the potential at a second node through the second controlling sub-circuit. Under the control of the potential at the second node, the voltage of the second voltage terminal can be outputted to the first and the second outputting terminals.

A data driver capable of displaying images with a substantially uniform brightness, an organic light emitting display device using the same, and a method of driving the organic light emitting display device. The data driver includes a plurality of current sink units for controlling predetermined currents to flow through data lines, a plurality of voltage generators for resetting values of gray scale voltages using compensation voltages generated when the predetermined currents flow, a plurality of digital-to-analog converters for selecting one gray scale voltage among the gray scale voltages as a data signal in response to bit values of the data supplied from the outside, and a plurality of switching units for supplying the data signal to the data lines. The predetermined currents may be set equal to pixel currents that correspond to a maximum brightness.