Related to is an array substrate, a liquid crystal display panel and a method for driving the liquid crystal display panel. In the array substrate, each pixel unit thereon comprises a main-area electrode, a sub-area electrode and a sharing capacitor. a control terminal of a sharing control switch connecting the sharing capacitor to the sub-area electrode is connected, via a first control switch, to a scan line correlated with an N.sup.th pixel unit which is arranged in a scanning direction and counted from a present pixel unit, and via a second control switch to a scan line correlated with the present pixel unit. Under a two-dimensional scanning mode, the first control switch is configured to be turned on when at least there is a scan signal on a scan line to which the first control switch is connected, and the second control switch is configured to be turned off when at least there is a scan signal on both a scan line to which the second control switch is connected and on a scan line to which a first control switch of the same stage as the second control switch is connected. Under a three-dimensional scanning mode, the first control switch is configured to be turned off when at least there is a scan signal on the scan line to which the first control switch is connected, and the second control switch is configured to be turned on when at least there is a scan signal on the scan line to which the second control switch is connected.

A method for driving a display panel having a variable refresh rate is disclosed. The method comprises detecting a condition that results in a charge accumulation in the display panel using an accumulated difference in time duration between frames of positive polarity and frames of negative polarity received from an image source. The DC imbalance is a result of a frame pattern comprising alternating frames of differing polarities, wherein frames of positive polarity within the frame pattern are of a different time duration than frames of negative polarity, and wherein the frame pattern results in an accumulation of charge in pixels of the display panel. The method also comprises correcting for the charge accumulation by disrupting the frame pattern.

A display substrate includes a first gate line configured to receive a first gate clock, a second gate line adjacent to the first gate line and configured to receive a second gate clock, a first data line configured to transfer a first data signal inverted according to the first gate clock and the second gate clock, where the first data signal has a first polarity, a second data line configured to transfer a second data signal inverted according to the first gate clock and the second gate clock, where the second data signal has a second polarity different from the first polarity, a first pixel including a first high sub pixel electrically connected to the first gate line and the first data line, and a first low sub pixel electrically connected to the first gate line and the second data line.

A ghost elimination method, a ghost elimination device and a display panel are provided. The ghost elimination method includes driving and displaying a display panel by taking a plurality of continuous frames of pictures as a period. In one period, motion compensation is performed on the front m frames of pictures, and the motion compensation is not performed on the remaining n frames of pictures, where m and n are both positive integers.

A liquid crystal display device (100) includes a first substrate (10), a second substrate (20) and a liquid crystal layer (30), and includes a plurality of pixels (Px). The first substrate includes a first electrode (11) and a second electrode (12) capable of generating a transverse electric field in the liquid crystal layer, and an alignment film (18) defining initial alignment axis azimuths (D1, D12), The first electrode includes at least one slit (11a). In each of the plurality of pixels, the alignment film includes a first region (18a) corresponding to the at least one slit of the first electrode and a second region (18b) corresponding to a portion of the first electrode other than the at least one slit. The initial alignment axis azimuth defined by the first region of the alignment film and the initial alignment axis azimuth defined by the second region of the alignment film are different from each other.

An object of the present invention is to suppress deterioration of display quality due to difference in wiring resistance and capacitance between the layers in a display device having a layered wiring structure. In a display device having a layered wiring structure of P layers, and employing a Q-column reversal driving method in which a polarity of a video signal is reversed every Q source bus lines (SL), the plurality of source bus lines SL are wired to the plurality of layers such that taking source bus lines (SL) of a number equal to a double of a least common multiple of P and Q as one group, the number of source bus lines (SL) to which positive video signals are applied matches the number of source bus lines (SL) to which negative video signals are applied in each of the layers in each of horizontal scanning periods.

The resolution of a low-resolution image is made high and a stereoscopic image is displayed. Resolution is made high by super-resolution processing. In this case, the super-resolution processing is performed after edge enhancement processing is performed. Accordingly, a stereoscopic image with high resolution and high quality can be displayed. Alternatively, after image analysis processing is performed, edge enhancement processing and super-resolution processing are concurrently performed. Accordingly, processing time can be shortened.

A display apparatus includes: a plurality of pixel blocks, each pixel block of the plurality of pixel blocks including a first pixel electrode connected to a first switching element and a second pixel electrode connected to a second switching element; gate lines which extend along a first direction and include a first gate line connected to the first switching element and a second gate line connected to the second switching element; and data lines which extend along a second direction intersecting the first direction. A gate voltage is applied to the first gate line before the second gate line, and the first pixel electrode of each of the pixel blocks displays a same color.

A display apparatus includes: a display panel which displays an image; a data driver which supplies a data voltage to the display panel in response to a polarity control signal, where the polarity control signal controls a polarity of the data voltage; a timing controller which outputs a polarity signal corresponding to a polarity of the data voltage; and a polarity converter which receives a common voltage from a common electrode of the display panel and the polarity signal from the timing controller, where the polarity converter outputs the polarity control signal to the data driver in response to a difference in voltage level between the common voltage from the common electrode and the polarity signal from the timing controller.

This application relates to systems, methods, and apparatus for optimizing the operations of a power converter of a display panel based on image data to be output by the display panel. The power converter can include one or more switches that can be activated or deactivated based on the image data in order to shift a power efficiency of the power converter. Power efficiency is shifted as a result of balancing an amount of charge necessary for a load with an amount of resistance created when activating switches of the power converter. Therefore, by dynamically altering a configuration of a power converter based on image data, power efficiency of the power converter can be improved.