G09G3/3614

DRIVING METHOD OF ARRAY SUBSTRATE, AND ARRAY SUBSTRATE

Disclosed are a driving method of an array substrate and an array substrate. The driving method of the array substrate controls a data drive signal line to output a first polarity data drive signal in a first time period and output a second polarity data drive signal in a second time period alternately. In the first time period, the first polarity data drive signal is output to drive the first sub-pixels of each pixel group to make the first sub-pixel of each pixel group to be a first polarity. In the second time period, the second polarity data drive signal is output to drive the second sub-pixel of each pixel group to make the second sub-pixel of each pixel group to be a second polarity. Polarities of sub-pixels of each column are the same.

Liquid crystal display device and electronic apparatus for preventing liquid crystal drive voltage from lowering
11615757 · 2023-03-28 · ·

A liquid crystal display device according to the present disclosure includes: a liquid crystal unit including a pixel electrode, a counter electrode facing the pixel electrode, and a liquid crystal layer sealed between the pixel electrode and the counter electrode; a first writing circuit configured to write a positive polarity video signal among video signals whose polarity changes periodically; and a second writing circuit configured to write a negative polarity video signal among the video signals whose polarity changes periodically. The liquid crystal unit, the first writing circuit, and the second writing circuit are provided for each pixel. The first writing circuit and the second writing circuit include transistors having conductivity types different from each other.

Source driver and output buffer thereof of liquid crystal display
11495189 · 2022-11-08 · ·

An output buffer is provided, which including an input circuit, output circuits, a first multiplexer, a second multiplexer and a demultiplexer. The input circuit is for generating a first control signal and a second control signal according to a feedback signal and an input signal. Each output circuit is controlled by a first gate signal and a second gate signal to provide a corresponding one of output signals. The first multiplexer is for providing the first control signal and the second control signal to one of the output circuits as the first gate signal and the second gate signal, respectively. The second multiplexer is for providing a first reference voltage and a second reference voltage as the first gate signal and the second gate signal, respectively, to other of the output circuits. The demultiplexer is for providing one of the output signals as the feedback signal.

Driving device and operation method thereof

A driving device and an operation method thereof are provided. The driving device includes a first driving circuit and a second driving circuit. The first driving circuit performs a display driving operation to a display panel. The second driving circuit performs a fingerprint sensing operation (including a sensor reset operation and an image capture operation) to the display panel according to a timing control signal of the first driving circuit. The fingerprint sensing operation is operated with a same frame polarity configuration rule. The operation of “the same frame polarity configuration rule” comprises fixing a relation between a first polarity configuration (which is the frame polarity configuration of the display panel when performing the sensor reset operation on a same fingerprint frame) and a second polarity configuration (which is the frame polarity configuration of the display panel when performing the image capture operation on the same fingerprint frame) whenever the fingerprint sensing operation is performed.

Display panel, driving method thereof and display apparatus
11488555 · 2022-11-01 · ·

This application discloses a display panel, a driving method thereof and a display apparatus. The display panel includes a substrate, the substrate being provided with a plurality of data lines, a plurality of gate lines, and a plurality of pixel units; and a gate driver chip, where each pixel unit includes subpixels of different colors; the gate driver chip outputs gate enabling signals to the gate lines to turn on the pixel units; and each row of pixel units includes a plurality of pixel groups, each pixel group includes a first column of subpixels and a second column of subpixels and a voltage of a gate enabling signal of the first column of subpixels is greater than that of a gate enabling signal corresponding to the second column of subpixels.

LIQUID CRYSTAL APPARATUS AND ELECTRONIC APPARATUS

A liquid crystal apparatus includes a liquid crystal layer, a pixel electrode provided in a display region and configured to be supplied with an image signal at a first frequency, and a first electrode provided in a region outside the display region and configured to be alternately supplied with a positive polarity potential with a potential higher than a predetermined potential and a negative polarity potential with a potential lower than the predetermined potential at a second frequency lower than the first frequency such that a positive polarity period in which the positive polarity potential is supplied and a negative polarity period in which the negative polarity potential is supplied have a same length.

Display driver
11615758 · 2023-03-28 · ·

A display driver includes a line latch circuit; a first D/A conversion circuit; a second D/A conversion circuit; a first amplifier circuit configured to initialize charges of a capacitor of a first switched capacitor circuit in a first initialization period and output a data voltage in a first output period; a second amplifier circuit configured to initialize charges of a capacitor of a second switched capacitor circuit in a second initialization period and output a data voltage in a second output period; and a control circuit. The control circuit is configured to end the second initialization period of the second amplifier circuit before display data is latched by the line latch circuit at a latch timing and an output of the first amplifier circuit changes.

Demultiplexer circuit, array substrate, display panel and device, and driving method

Provided are a demultiplexer circuit, an array substrate, a display panel and device, and a driving method. The demultiplexer circuit includes multiple demultiplexers, each demultiplexer includes at least two switching transistor groups, and each switching transistor group includes at least two switching transistors. Sources of the at least two switching transistors in a same switching transistor group are electrically connected to each other, drains of the at least two switching transistors in the same switching transistor group are electrically connected to each other. Input ends of the at least two switching transistor groups in a same demultiplexer are electrically connected to each other. In the same switching transistor group, the common source is electrically connected to the input end, the common drain is electrically connected to the output end, and at least two control ends are electrically connected to gates of the switching transistors in a one-to-one correspondence.

COMMON ELECTRODE PATTERN, DRIVING METHOD, AND DISPLAY EQUIPMENT
20230089652 · 2023-03-23 · ·

A common electrode pattern, a driving method and a display equipment. By performing common voltage compensations for all positive-polarity pixels and all negative-polarity pixels through two common electrode units, respectively, the difference between the reduction degrees of the pixel potential of the display equipment at different refresh frequencies can be effectively reduced, so that the brightness of the screen displayed by the display equipment at different refresh frequencies tend to be consistent, thereby improving the phenomenon of screen flickering.

SHIFT REGISTER AND DRIVE METHOD THEREOF, AND GATE DRIVE CIRCUIT

The present disclosure provides a shift register, a drive method thereof, and a gate drive circuit. The shift register includes an input circuit, a reset circuit, a first output circuit, and a second output circuit. The input circuit is configured to provide an input signal from an input terminal to a first node. The reset circuit is configured to provide a first voltage from a first voltage terminal to the first node under the control of a reset signal from a reset signal terminal. The first output circuit is configured to output from a first output terminal one of a first clock signal and a second clock signal as a first scan signal. The second output circuit is configured to output from a second output terminal the other of the first clock signal and the second clock signal as a second scan signal.