A second substrate has detection electrodes of a touch panel, each of pixels has a pixel electrode and a counter electrode, the counter electrode is divided into a plurality of blocks, the counter electrodes of the respective divided blocks are commonly provided for the respective pixels of the plurality of display lines in series, and the counter electrodes also serve as scanning electrodes of the touch panel, and a counter electrode selector circuit that selects the counter electrodes. The counter electrode selector circuit includes an address decoder circuit that selects the counter electrodes of the respective blocks for a given period, and a selector circuit that applies a touch panel scanning voltage to the counter electrode of the block selected by the address decoder circuit, and applies a counter voltage to the counter electrodes of the blocks not selected by the address decoder circuit.

A display device and method of driving the same are disclosed. The display device that transmits signals between a system board section and a circuit board section through an interface and uses Panel Self-Refresh (hereinafter, abbreviated as ‘PSR’) to reduce power consumption, the circuit board section comprising a PSR controller that, when a PSR On signal is supplied from the system board section, changes the operating frequency of a gate driver and data driver to a frequency higher than a reference frequency for driving the panel with PSR On, set by the system board section.

An object of the present invention is to realize a liquid crystal display device of a field sequential system which is capable of preventing occurrence of color shift and flicker. One frame period is divided into a plurality of fields, the number of which is greater than the number of lighting patterns. Provided are a liquid crystal state value acquiring unit (131) configured to obtain a liquid crystal state value at an end time of a display field based on an input gradation value in the display field and a liquid crystal state value at an end time of a previous field (one field before the display field) (a gradation value corresponding to an aligned state of liquid crystal molecules), and an application gradation value acquiring unit (133) configured to obtain an application gradation value in the display field by correcting an input gradation value in the display field based on a liquid crystal state value at the end time of the previous field. The application gradation value acquiring unit (133) obtains an application gradation value such that display luminance in each field becomes display luminance corresponding to the input gradation value.

Embodiments of the present disclosure provide a pixel circuitry. The pixel circuitry includes a data write-in circuit, an initialization circuit, a sense circuit, a first capacitor, a second capacitor, a drive transistor, and a data signal supply circuit. The data write-in circuit supplies a data signal to a first node according to a first control signal. The initialization circuit supplies an initialization signal to a sense line according to a second control signal. The sense circuit couples a second node to the sense line according to the first control signal. The data signal supply circuit reads the voltage of the sense line according to a third control signal, determines a threshold voltage of the drive transistor according to the read voltage, and corrects an original data signal according to the threshold voltage to supply the corrected original data signal to the data line.

Systems, apparatuses, and methods for performing asynchronous memory clock changes on multiple displays are disclosed. From time to time, a memory clock frequency change is desired for a memory subsystem storing frame buffer(s) used to drive pixels to multiple displays. For example, when the real-time memory bandwidth demand differs from the memory bandwidth available with the existing memory clock frequency, a control unit tracks the vertical blanking interval (VBI) timing of a first display. Also, the control unit causes a second display to enter into panel self-refresh (PSR) mode. Once the PSR mode of the second display overlaps with a VBI of the first display, a memory clock frequency change, including memory training, is initiated. After the memory clock frequency change, the displays are driven by the frame buffer(s) in the memory subsystem at an updated frequency.

A control chip configured to be coupled with a backlight driving chip and a display panel is provided. The control chip includes a storage element and a processing circuit. The storage element is configured to store a predetermined vertical refresh rate of the display panel. The processing circuit is coupled with the storage element, and is configured to provide a switching signal to the backlight driving chip so that the backlight driving chip enables a backlight module according to the switching signal. A frequency of the switching signal is equal to the predetermined vertical refresh rate. If the processing circuit has not received a vertical refresh starting pulse for more than a predetermined frame time corresponding to the predetermined vertical refresh rate, the processing circuit increases the frequency of the switching signal.

According to various embodiments of the present disclosure, a system and method for providing fast response time performance with low latency in Liquid Crystal Displays (LCDs) are described. In some embodiments, an Information Handling System (IHS) may include a controller and a memory coupled to the controller, the memory having program instructions stored thereon that, upon execution, cause the controller to receive LCD display capability information from a display device, and determine from the received capability information, that a video stream sent to the display device has a lower frame rate than the capabilities of the display device. Using this information the instructions then increase the frame rate of the video stream by repeating each frame during a current time window of the frame.

Disclosed are an information display method, a terminal device, and a readable storage medium. The information display method includes: obtaining an information type of each of a plurality of to-be-displayed information; in response to the information type comprising a target information type, obtaining a first refresh frequency of a target to-be-displayed information corresponding to the target information type, and determining a first display frequency of a display screen according to the first refresh frequency; and displaying the plurality of to-be-displayed information according to the first display frequency.

Refreshing displays using on-die cache, including: determining that a static display condition has been met; storing, in cache memory of a processor, first display data; and displaying the first display data from the cache memory.

Disclosed are an information display method, a terminal device, and a readable storage medium. The information display method includes: obtaining an information type of each of a plurality of to-be-displayed information; in response to the information type comprising a target information type, obtaining a first refresh frequency of a target to-be-displayed information corresponding to the target information type, and determining a first display frequency of a display screen according to the first refresh frequency; and displaying the plurality of to-be-displayed information according to the first display frequency.