The disclosure provides a display equipment, a brightness compensation device, and a brightness compensation method. The brightness compensation device includes a variable refresh rate (VRR) detection circuit and a control circuit. The VRR detection circuit and the control circuit receive a video stream from a video source device, and the video stream includes a VRR video frame. The VRR detection circuit detects a blanking period of the VRR video frame and generates a detection result. The control circuit outputs the frame data of the VRR video frame to the display device during the valid data period of the VRR video frame. The control circuit repeatedly outputs the frame data of the VRR video frame to the display device during the blanking period of the VRR video frame according to the detection result until the blanking period ends.

A display method, a display device, a display system, and a storage medium are provided. The display method includes: obtaining a first fixation coordinate transmitted by an image acquisition device, and obtaining a second fixation coordinate and a current frame of image that are transmitted by a first processor; performing refresh and display by using the current frame of image; determining a type of the current frame of image, and determining, based on the type, whether the first fixation coordinate changes abnormally; and performing refresh and display by using a previous frame of image for non-fixation region in a case that the first fixation coordinate changes abnormally, and performing refresh and display by using a next frame of image transmitted by the first processor in a case that the first fixation coordinate does not change abnormally.

A pixel driving circuit, a pixel unit and a driving method therefor, an array substrate, and a display device for reducing mura phenomenon comprise: a data write sub-circuit for transmitting signals input by the data voltage terminal to a first node; an input and read sub-circuit for transmitting a signal input from a signal transmission terminal to a second node, or reading an electric signal of the second node to the signal transmission terminal; and an output control sub-circuit for transmitting a signal of a first voltage terminal to a drive sub-circuit, and transmitting a driving signal output by the drive sub-circuit to a driven circuit, wherein the drive sub-circuit outputs the driving signal under control of the signal of the first node and the signal of the first voltage terminal.

A display method, a display device, a display system, and a storage medium are provided. The display method includes: obtaining a first fixation coordinate transmitted by an image acquisition device, and obtaining a second fixation coordinate and a current frame of image that are transmitted by a first processor; performing refresh and display by using the current frame of image; determining a type of the current frame of image, and determining, based on the type, whether the first fixation coordinate changes abnormally; and performing refresh and display by using a previous frame of image for non-fixation region in a case that the first fixation coordinate changes abnormally, and performing refresh and display by using a next frame of image transmitted by the first processor in a case that the first fixation coordinate does not change abnormally.

Provided are a display panel and manufacturing method thereof, control method and display apparatus. The display panel includes a first substrate including first base substrate and driving structure layer, and a second substrate including second base substrate and black matrix layer, driving structure layer includes multiple switching transistors, the display panel includes multiple pixel units, each pixel unit includes a switching transistor. One side of black matrix layer close to first substrate is provided with multiple groove structures corresponding to multiple pixel units one-to-one. Orthographic projection of black matrix layer on first base substrate covers those of multiple switching transistors on first base substrate, and orthographic projection of the groove structure on first base substrate at least partially overlaps with that of a channel region of switching transistor in corresponding pixel unit on first base substrate to enable light meeting preset wavelength condition to be incident into the display panel.

Embodiments of the present disclosure provide a pixel circuitry. The pixel circuitry includes a data write-in circuit, an initialization circuit, a sense circuit, a first capacitor, a second capacitor, a drive transistor, and a data signal supply circuit. The data write-in circuit supplies a data signal to a first node according to a first control signal. The initialization circuit supplies an initialization signal to a sense line according to a second control signal. The sense circuit couples a second node to the sense line according to the first control signal. The data signal supply circuit reads the voltage of the sense line according to a third control signal, determines a threshold voltage of the drive transistor according to the read voltage, and corrects an original data signal according to the threshold voltage to supply the corrected original data signal to the data line.

An optical device (10) includes a first substrate (11) and a second substrate (12) facing each other, a liquid crystal component (13) between the first substrate (11) and the second substrate (12), a first electrode (18) and a second electrode (19) located on the first substrate (11) on the second substrate (12) side, and a first alignment layer (14) that is located on the first substrate (11) on the second substrate (12) side and controls the alignment state of liquid crystal molecules in the liquid crystal component (13), wherein an interface between the liquid crystal component (13) and the first alignment layer (14) forms a non-glide weak anchoring interface (17).

A display system receives first timing information prior to the display system entering a panel self-refresh (PSR) mode. The display system supports a range of refresh rates. Prior to the display system entering the PSR mode, first timing information indicating a first refresh rate that is lower than a maximum refresh rate supported by the display system is received by the display system. The display system then refreshes images at a second refresh rate that is less than or equal to the first refresh rate using a frame stored in a buffer prior to entering the PSR mode. In some cases, the processing unit also receives second timing information from the display system in response to initiating an exit from a panel self-refresh (PSR) mode. The second timing information indicates a current scanout line that is used to schedule transmission of a subsequent frame.

In multi-display systems, such as video walls, comprising a control computing system providing content to multiple display computing systems driving a plurality of displays, the refresh rates of the displays can drift over time. This drift can introduce display artifacts, which can make for an unpleasant viewing experience. To counteract display refresh drift, a control system periodically compares display refresh timestamps of the individual display systems to a reference display refresh timestamp of a reference display system. If the difference exceeds a threshold, the control system determines clock adjustment information that is sent to the display system exhibiting drift. The display system utilizes the clock adjustment information to adjust the frequency of a display system clock, which can be done by writing the clock adjustment information to registers that control the behavior of a phase-locked loop that generates the clock used by display refresh circuitry.

A pixel driving circuit, a pixel driving method, an array substrate and a display device are provided. The pixel driving circuit includes a plurality of pixel regions; a pixel electrode array; and a thin film transistor switch, where at least one thin film transistor switch is arranged in each pixel region; the polarities of input voltage signals to two adjacent pixel electrodes are opposite in a same row of pixel electrodes; M rows of pixel electrodes are divided into Q pixel groups, including a first pixel group, a second pixel group and (Q−2) third pixel groups located between the first pixel group and the second pixel group, and each third pixel group includes at least q rows of pixel electrodes; and in the same column of pixel electrodes, the polarities of input voltage signals to the pixel electrodes in the same pixel group are the same, and the polarities of input voltage signals to the pixel electrodes of two adjacent pixel groups are opposite.