A unit (10; 11; 12; 13) used to control a segment liquid crystal display (15; 16). The segment liquid crystal display (15; 16) includes at least a backplane electrode (20) and at least a front plane electrode (25) both associated with a same segment of the segment liquid crystal display (15; 16). The unit (10; 11; 12; 13) includes a controller (30; 40; 50) in order to generate a pulse-width-modulated control signal (35) that has two voltage levels and a variable duty cycle. The unit (10; 1; 12; 13) further includes an integrator (60; 61) to integrate the pulse-width-modulated control signal (35) and to provide an integrated control signal (90) which has more than two discrete voltage levels corresponding to different variable duty cycle values. An output of the unit (10; 11; 2; 13) supplies the integrated control signal (90) to the at least a backplane electrode (20) or to the at least a front plane electrode (25) so that visibility of the same segment in the segment liquid crystal display (15; 16) can be controlled. By having a pulse-width-modulated control signal (35) with only two voltage levels and different duty cycle values generated by the controller (30; 40; 50), and by having the integrator (60; 61) integrating said pulse-width-modulated control signal (35), more than two different discrete voltage levels are generated to control the at least a backplane electrode (20) or at least a front plane electrode (25) without the need to use an application specific segment liquid crystal interface in the unit (10; 11; 12; 13), thereby abating the cost of implementation of the unit (10; 11; 12; 13).

A flat panel display includes a display panel comprising a display area and a non-display area which is disposed on a outside of the display area and has at least one recess on one end side thereof; a driving substrate disposed on a rear surface of the display panel; and at least one connection member connected to the display panel and the driving substrate through at least one recess.

A shift register unit and a method of driving the same, a gate driving circuit and a display device are provided. The first pull-up circuit of the shift register is configured to output a signal of the first clock signal end to the first signal output end under a control of the pull-up node. The second pull-up circuit is configured to output the signal of the first clock signal end to the second signal output end under a control of the pull-up node. The first pull-down circuit is configured to pull down a potential of the pull-up node and a potential of the first signal output end to the potential of the second voltage end under a control of the pull-down node. The second pull-down circuit is configured to pull down a potential of the second signal output end to the potential of the second voltage end under a control of the pull-down node.

A target image can be analyzed determine a respective level of visual saliency for each of a plurality of information presented in the target image. At least a first sub-frame update for a display panel can be determined, the at least first sub-frame update providing at least a partial rendering of the target image on the display panel, the at least partial rendering of the target image providing the information presented in the target image that is determined to have a highest level of visual saliency from among the plurality of information. The at least first sub-frame update can be applied to the display panel.

A liquid crystal drive device includes a common driver configured to sequentially output a scanning signal having a plurality of voltage levels to a plurality of common wirings in a time division manner, a segment driver configured to output a display signal having a plurality of voltage levels to a plurality of segment wirings, and a contrast adjustment unit configured to generate contrast adjustment periods that are inserted into all duty periods, and output, to the common driver and the segment driver, a contrast control signal to control the timing of when the contrast adjustment periods are inserted into the duty periods in synchronization with the timing of the scanning signal and the display signal. The scanning signal and the display signal are output at an identical potential when a contrast adjustment period is indicated by the output of the contrast control signal.

In one example, a display backlight includes organic light emitting diodes patterned in a segmented manner, and one or more spacers spaced between the white organic light emitting diodes.

Disclosed is a driving method of a liquid crystal display panel. Area division is implemented to obtain at least three division areas for individually providing a compensation signal voltage to each division area according to the difference of the actual brightnesses and the target brightnesses, and with the compensation signal voltage, implementing enhancement to a data signal voltage corresponded with a sub pixel, of which a difference of the data signal voltage (V+) in a positive polarity driving cycle or the data signal voltage (V) in a negative polarity driving cycle and the common voltage (VCOM) is smaller, and implementing abatement to a data signal voltage corresponded with a sub pixel, of which a difference of the data signal voltage (V+) in the positive polarity driving cycle or the data signal voltage (V) in the negative polarity driving cycle and the common voltage (VCOM) is larger.

A liquid crystal panel includes a first substrate, a second substrate spaced apart from the first substrate, and a liquid crystal layer between the first substrate and the second substrate. The second substrate includes an ITO layer facing toward the liquid crystal layer, the ITO layer comprises at least one first pixel electrode layer, at least one common electrode layer, and at least one second pixel electrode layer spaced apart from each other. A first voltage difference between the first pixel electrode layer and the common electrode layer is different from a second voltage difference between the second pixel electrode layer and the common electrode layer. In this way, the intensity of the horizontal electrical field above the common electrode layer is enhanced such that the transmission rate of the liquid crystal panel may be increased.

A display device. The display device comprises: a housing (01) having an outlet (06); a flexible display panel (02) located inside the housing (01). At least a portion of the flexible display panel (02) can be pulled out from the outlet (06), and in a case where the flexible display panel (02) is pulled out, a region located outside the housing (01) is a front end region (02a) of the flexible display panel (02), and a region located inside the housing (01) is a rear end region (02b) of the flexible display panel (02). An extending direction from the front end region (02a) to the rear end region (02b) is a direction from front to rear of the flexible display panel (02). The display device further comprises a detection calculation unit (03) configured to detect and calculate an area of the front end region (02a); and a controller signally connected with the detection calculation unit (03) and the flexible display panel (02), and configured to receive the area of the front end region (02a) output from the detection calculation unit (03) and control only the front end region (02a) displaying images.

An object is to reduce parasitic capacitance of a signal line included in a liquid crystal display device. A transistor including an oxide semiconductor layer is used as a transistor provided in each pixel. Note that the oxide semiconductor layer is an oxide semiconductor layer which is highly purified by thoroughly removing impurities (hydrogen, water, or the like) which become electron suppliers (donors). Thus, the amount of leakage current (off-state current) can be reduced when the transistor is off. Therefore, a voltage applied to a liquid crystal element can be held without providing a capacitor in each pixel. In addition, a capacitor wiring extending to a pixel portion of the liquid crystal display device can be eliminated. Therefore, parasitic capacitance in a region where the signal line and the capacitor wiring intersect with each other can be eliminated.