The present disclosure relates to electronic displays and display components, specifically to a method of addressing more pixels with a smaller number of driver outputs while also allowing very narrow frames on three sides of a display. It further discloses a display driver integrated circuit capable of providing the signals required for the disclosed addressing method and display systems capable of being addressed by the disclosed method and display driver integrated circuit.

A display device includes: pixel electrodes including a first pixel electrode and a second pixel electrode adjacent to the first pixel electrode in a first direction; switching elements including a first switching element coupled to the first pixel electrode and a second switching element coupled to the second pixel electrode; gate lines including a first gate line coupled to the first switching element and a second gate line coupled to the second switching element; a gate driver supplying a gate signal to the gate lines; and drive electrodes including a first drive electrode and a second drive electrode adjacent to the first drive electrode in the first direction. The first drive electrode overlaps the first and second pixel electrodes, and the second gate line. The second drive electrode overlaps the first gate line. The gate driver supplies the gate signal to the first and second gate lines simultaneously.

The present disclosure relates to a shift register unit having a cascade input terminal, a cascade output terminal and a scan output terminal. The shift register unit may include a first shift circuit, a second shift circuit, an input circuit, and a control circuit. The input circuit may be configured to provide an input signal from the cascade input terminal to an input terminal of the first shift circuit under control of an input clock terminal. The control circuit may be configured to control connection of an output terminal of the first shift circuit and an input terminal of the second shift circuit based on a signal at a first control terminal.

A display device includes a level shifter and a gate driving circuit that can reduce differences in characteristics among gate signals to improve image quality by controlling a signal waveform of a first clock signal of the m number of clock signals different from a signal waveform of an m-th clock signal when m number of gate signals is output by using m number of clock signals.

A liquid crystal display (LCD) and a method for compensating current leakage of the LCD are provided. The LCD includes a thin film transistor (TFT) array having a plurality of TFTs, a gate driver configured to provide a scan signal, a source driver configured to provide a data signal, and a timing controller electrically connected to the gate driver and the source driver. The timing controller is configured to adjust a current refresh frequency according to a current frame rate and to transfer a control signal to the gate driver when the current refresh frequency is lower than a threshold frequency such that the gate driver increase a charging time of the plurality of TFTs according to the control signal.

To suppress fluctuation in the threshold voltage of a transistor, to reduce the number of connections of a display panel and a driver IC, to achieve reduction in power consumption of a display device, and to achieve increase in size and high definition of the display device. A gate electrode of a transistor which easily deteriorates is connected to a wiring to which a high potential is supplied through a first switching transistor and a wiring to which a low potential is supplied through a second switching transistor, a clock signal is input to a gate electrode of the first switching transistor, and an inverted clock signal is input to a gate electrode of the second switching transistor. Thus, the high potential and the low potential are alternately applied to the gate electrode of the transistor which easily deteriorates.

A display panel driving method, a drive circuit thereof, and a display device. The method comprises: when determined that the picture to be displayed belongs to a high power consumption display picture, providing a touch control and display integrated circuit and power supply management circuit of the display panel with a second reference voltage that is amplified by a first reference voltage and that is provided by an external voltage source, and driving each pixel to ensure the normal display of the high power consumption display picture; and when determined that the picture to be displayed belongs to a low power consumption display picture, directly providing the first reference voltage to the touch control and display integrated circuit and power supply management circuit of the display panel, and driving each pixel within the display panel so as to ensure the normal display of the low power consumption picture.

An object is to provide a semiconductor device which can suppress characteristic deterioration in each transistor without destabilizing operation. In a non-selection period, a transistor is turned on at regular intervals, so that a power supply potential is supplied to an output terminal of a shift register circuit. A power supply potential is supplied to the output terminal of the shift register circuit through the transistor. Since the transistor is not always on in a non-selection period, a shift of the threshold voltage of the transistor is suppressed. In addition, a power supply potential is supplied to the output terminal of the shift register circuit through the transistor at regular intervals. Therefore, the shift register circuit can suppress noise which is generated in the output terminal.

A first flipflop outputs a first signal synchronized with a first clock signal, a second flipflop outputs a second signal synchronized with a second clock signal, and a third flipflop outputs a third signal synchronized with a third clock signal. The second flipflop includes first to fifth transistors. In the first transistor, the second clock signal is input to a first terminal and the second signal is output from a second terminal. In the second transistor, a first signal is input to a first terminal, a second terminal is electrically connected to a gate of the first transistor, and the first clock signal is input to a gate. In the third transistor, the third signal is input to a first terminal, a second terminal is electrically connected to the gate of the first transistor, and the third clock signal is input to a gate.

The present disclosure relates to a driving unit, including a first driving sub-circuit, a second driving sub-circuit, and a driving control circuit. The first driving sub-circuit includes first switching elements, configured to output a first signal to the driving unit in response to a control signal from the driving control circuit. The second driving sub-circuit includes one or more second switching elements, and at least one of the second switching elements is configured to output a second signal to the driving unit in response to the control signal. The driving control circuit is configured to output the control signal at a control signal output terminal. Each of the first switching elements and second switching elements includes a transistor. Control signal input terminals of the first switching elements are coupled to the control signal output terminal through a control signal input line having a ring structure.