Disclosed is a shift register including a first input sub-circuit, configured to receive a first input signal from a first input terminal and output a blanking output control signal to a first node in a blanking period of time of a frame; a second input sub-circuit, configured to receive a second input signal from a second input terminal and output a display output control signal to the first node in a display period of time of the frame; an output sub-circuit, configured to output a composite output signal via an output terminal under control of the first node, the composite output signal including a display output signal outputted in a display period of time and a blanking output signal outputted in a blanking period of time which are independent of each other.

An object is to provide a semiconductor device with improved operation. The semiconductor device includes a first transistor, and a second transistor electrically connected to a gate of the first transistor. A first terminal of the first transistor is electrically connected to a first line. A second terminal of the first transistor is electrically connected to a second line. The gate of the first transistor is electrically connected to a first terminal or a second terminal of the second transistor.

A display panel and a display device. The display panel includes at least two controlled modules and a signal wire connected to the at least two controlled modules. The signal wire is configured to receive a drive signal sent by a drive module and transmit the drive signal to the at least two controlled modules. The signal wire includes a first path wire section and a second path wire section. A first end of the first path wire section and a first end of the second path wire section are configured to receive the same drive signal. The first path wire section is configured to sequentially transmit the drive signal to the at least two controlled modules in a first preset sequence. The second path wire section is configured to sequentially transmit the drive signal to the at least two controlled modules in a second preset sequence.

A display device includes: a display substrate including a display area and a non-display area adjacent to each other; and an opposing substrate opposing the display substrate. The display substrate includes: a pixel in the display area; a gate driver at the non-display area and including a gate and data wiring; an organic layer on the gate and data wiring; a column spacer on the organic layer; a connection portion connected to the gate and data wiring at contact holes respectively exposing the gate and data wiring; and a protective layer on the connection portion. In a top plan view, the protective layer has a same shape as a shape of the connection portion. The opposing substrate includes a black matrix at the display area to define a pixel area of the pixel and at the non-display area to define the display area and the non-display area.

A display apparatus includes a display panel driven based on a first gate clock and a second gate clock, a clock supply circuit including a first output terminal for an output of the first gate clock and a second output terminal for an output of the second gate clock, supplying the first output terminal with one of a gate high voltage and a gate low voltage as a first test voltage, and supplying the second output terminal with the other of the gate high voltage and the gate low voltage as a second test voltage, for a first time immediately after a system power is applied thereto, a power generator generating the gate high voltage and the gate low voltage and supplying the gate high voltage and the gate low voltage to the clock supply circuit, and an overcurrent detector receiving a flag signal to recognize overcurrent from the power generator to shut down the power generator, when the first output terminal and the second output terminal are short-circuited with each other at the first time interval.

In a GOA circuit and a display panel provided by embodiments of the present application, a reset module is provided in each level of GOA units, so that each level of the GOA units can output a high potential before an end of a frame, all gates in a display area are turned on, and a charge of all pixels in the display area is discharged; after that, each level of the GOA units outputs a low potential, and all of the gates in the display area are set to the low potential.

An input detection device includes a substrate, and a plurality of detection electrodes that are disposed on a plane parallel to the substrate. The detection electrode includes a plurality of first conductive wires along a first direction, and a plurality of opening portions disposed between the first conductive wires. The first conductive wire includes a first wide portion, and a first narrow portion with a width smaller than a width of the first wide portion.

A display device includes: a first pixel group including first, second and third pixels arranged adjacent to each other and positioned successively along a first direction; and a second pixel group including fourth, fifth and sixth pixels arranged adjacent to the first pixel group and positioned successively along the first direction. Multiple ones of each of the first pixel group and the second pixel group are arranged in an alternating manner along both the first direction and a second direction intersecting the first direction. The second pixel and the fifth pixel face each other with respect to a first gate line while being connected to the first gate line, the first pixel and the fourth pixel face each other with respect to a second gate line while being connected to the second gate line.

A liquid crystal display panel is provided by the present invention, which comprises a plurality of data lines, a plurality of scanning lines, and a plurality of pixel units; wherein the pixel units of each column comprise two types of pixel units disposed interleaved, the adjacent pixel units are different types, and each of the data lines connects to the same type of adjacent pixel units. The present invention completes driving a plurality of adjacent row pixel units at the same time by making data lines connect with the same type pixel units.

Provided is a display device, including: a plurality of gate lines extending in a first direction; a plurality of source lines extending in a second direction; a gate driver configured to output a gate signal; and a plurality of gate lead-out lines extending in the second direction and being configured to transmit the gate signal to the plurality of gate lines, in which each of the plurality of gate lines is electrically connected to at least one of the plurality of gate lead-out lines, and at least one of the plurality of gate lines is electrically connected to at least two of the plurality of gate lead-out lines.