A display device includes: pixel electrodes including a first pixel electrode and a second pixel electrode adjacent to the first pixel electrode in a first direction; switching elements including a first switching element coupled to the first pixel electrode and a second switching element coupled to the second pixel electrode; gate lines including a first gate line coupled to the first switching element and a second gate line coupled to the second switching element; a gate driver supplying a gate signal to the gate lines; and drive electrodes including a first drive electrode and a second drive electrode adjacent to the first drive electrode in the first direction. The first drive electrode overlaps the first and second pixel electrodes, and the second gate line. The second drive electrode overlaps the first gate line. The gate driver supplies the gate signal to the first and second gate lines simultaneously.

An interface circuit comprises a timing signal generating unit that generates a timing signal indicating a timing to switch between a data input period and a non-input period, a plurality of driver error detection circuits that detects an error in source drivers, a selector circuit that selects one of the driver error detection circuits in the non-input period and that outputs a driver error detection signal indicating an error detection result, an input error detection circuit that detects an input error of a data signal and outputs an input error detection signal indicating the result, an OR circuit that outputs an OR of the driver error detection signal and the input error detection signal, and a signal output unit connected to an output part of the OR circuit.

A display driving device and an anti-interference method thereof are provided. A timing controller outputs a data signal. A source driver detects an interference event according to the data signal, and outputs a feedback signal to the timing controller in response to the detection result of the interference event. The timing controller adjusts the signal strength of the data signal according to the feedback signal.

Disclosed are a display driver for a low power driving and a timing controller for the display device. The display device may include the timing controller configured to transmit a packet to which one of first option information corresponding to a static pattern or second option information corresponding to a dynamic pattern is applied, and a source driver configured to receive the packet and to perform a low power mode corresponding to the static pattern based on the first option information or adaptive charge sharing corresponding to the dynamic pattern based on the second option information.

A display device includes a display panel having a plurality of sensing channels connected to a plurality of subpixels to detect a driving characteristic value, a data driving circuit including an analog-to-digital converter converting a sensing voltage detected through the plurality of sensing channels into digital sensing data and converting a subpixel driving voltage detected through at least one dummy channel into digital dummy sensing data, and a timing controller calculating an intensity of a current flowing through the data driving circuit based on the digital dummy sensing data transferred from the data driving circuit and compensating for image data transferred to the data driving circuit.

Disclosed is a gamma amplifier which includes a first amplification device that receives a first input signal during a first track period in a first time period, compensates for a first offset voltage from the first input signal during a first compensation period in the first time period, and generates a first output signal during a second time period after the first time period based on a control signal, and a second amplification device that receives a second input signal during a second track period in the second time period, compensates for a second offset voltage from the second input signal during a second compensation period in the second time period, and generates a second output signal during a third time period after the second time period based on the control signal and processing circuitry configured to generate the control signal.

A display device including a display unit which has a plurality of pixels and a plurality of driving lines for driving the plurality of pixels; a driving circuit which drives the plurality of pixels through the plurality of driving lines; and a control unit which adjusts a driving capability of the driving circuit according to the number of simultaneous driving lines of the driving circuit.

A display device includes: a display panel including a plurality of pixels connected to a plurality of scan lines and a plurality of data lines, respectively; a scan driver, which provides a scan signal to the pixels through the scan lines; a data driver, which provides a data voltage to the pixels through the data lines; and a controller, which controls the scan driver and the data driver, and receives input image data at a variable input frame frequency. The controller determines whether a gray scale value of the input image data is included in any range of a first gray scale range and a second gray scale range different from the first gray scale range, and dithers the input image data when it is determined that the gray scale value of the input image data is included the first gray scale range

A display device is provided and includes signal line; pixel electrode; drive electrode opposed to pixel electrode; scanning lines; and display periods and a detection period in frame, wherein during one of display periods, common voltage is applied to drive electrode, scanning signal is applied to some scanning lines, pixel signal is applied to pixel electrode, wherein, during detection period, AC drive or pulse signal is applied to drive electrode, AC drive or pulse signal having pulses, wherein pulses during the detection period is less than number of some of scanning signal lines.

A display device includes a display substrate, a plurality of source drive circuit elements, gate drive circuits, and a plurality of gate connection lines. The plurality of gate connection lines pass through inter-element regions between the source drive circuit elements in plan view, and pass through mounting regions. Gate terminals connected to the gate connection lines are formed at positions facing the inter-element regions in a direction from the inter-element regions toward an FPC (Y2 direction).