Patent classifications
G09G3/3685
Data driving circuit, method for detecting noise of display signal, and display apparatus
The present embodiment provides a technology for sensing a common mode voltage in the positive line and negative line of a transmission line for image data and determining whether noise occurs in the image data transmitted through the transmission line by comparing the common mode voltage with a set reference voltage.
Method for driving semiconductor device
The resolution of a low-resolution image is made high and a stereoscopic image is displayed. Resolution is made high by super-resolution processing. In this case, the super-resolution processing is performed after edge enhancement processing is performed. Accordingly, a stereoscopic image with high resolution and high quality can be displayed. Alternatively, after image analysis processing is performed, edge enhancement processing and super-resolution processing are concurrently performed. Accordingly, processing time can be shortened.
Display device, CMOS operational amplifier, and driving method of display device
A display device including a display unit which has a plurality of pixels and a plurality of driving lines for driving the plurality of pixels; a driving circuit which drives the plurality of pixels through the plurality of driving lines; and a control unit which adjusts a driving capability of the driving circuit according to the number of simultaneous driving lines of the driving circuit.
Touch display device
A touch display device according to one embodiment of the present disclosure includes a first drive integrated circuit configured to output a source signal and receives a touch sensing signal, and a second drive integrated circuit configured to output the source signal, wherein the first drive integrated circuit outputs the source signal in a display mode and receives the touch sensing signal in a touch sensing mode, the second drive integrated circuit outputs the source signal in the display mode, and the first drive integrated circuit and the second drive integrated circuit have the same resistance value in the display mode.
DISPLAY PANEL
A display panel including a plurality of pixel units, a plurality of source lines, a plurality of gate lines and a plurality of common electrode lines is provided. The pixels units are arranged in array. The array includes a plurality of columns and a plurality of rows. The source lines are respectively coupled with the pixel units disposed in a same column of the columns. The gate lines are respectively coupled with the pixel units disposed in a same row of the rows. The common electrode lines and gate lines extend parallelly with each other. At least one of the source date lines, the gate lines and the common electrode lines has the line widths varied along the extension direction thereof.
ROLLABLE DISPLAY DEVICE AND ELECTRONIC DEVICE INCLUDING THE SAME
A rollable display device includes a rollable structure including a plurality of unit structures, the rollable structure being configured to be rolled and unrolled based on the unit structures, and a display panel structure attached to the rollable structure, wherein respective widths of the unit structures increase in a first direction from a first side of the rollable structure to an opposite second side of the rollable structure.
Method For Controlling Offset Voltage In Display Device, Display Device, and Storage Medium
The present application provides a method for controlling an offset voltage in a display device, a display device and a storage medium. The method for controlling an offset voltage in a display device comprises: generating a chopper signal based on at least one of a data output control signal and a polarity inversion control signal; and, controlling, according the chopper signal, the polarity of an offset voltage of an operational amplifier in the display device, so that the offset voltage is equivalently eliminated within at least one of a design space range and a design time range. By using the control method of the present application, without using large-size transistors and providing more signals, the display effect can be ensured and the size of the chip can also be reduced.
LOAD DRIVING CIRCUIT, DISPLAY DRIVER, DISPLAY APPARATUS AND SEMICONDUCTOR DEVICE
Provided is an output amplifier having: a push-pull output-stage formed by first and second output-stage transistors; and a detection circuit detecting an abnormal output current output by the output amplifier and including: a coupling circuit, generating first and second currents mirroring current flowing in the first output-stage transistor and third and fourth currents mirroring current flowing in the second output-stage transistor, coupling the first and third currents at a first output node, outputting a first voltage at the first output node, coupling the second and fourth currents at a second output node, and outputting a second voltage at the second output node; and a determination circuit, outputting a determination signal indicating normality of an output current based on the first and second voltages. The coupling circuit generates the first to fourth currents. In the reference state, the third current > the first current, the second current > the fourth current.
Display device and a method for driving the same
A display device includes: a common electrode and a pixel electrode that includes a horizontal stem, a vertical stem, and a branch. A pixel of the branch includes a first branch that extends in a first diagonal direction from the horizontal stem and the vertical stem, and a second branch that extends in a second diagonal direction from the horizontal stem and the vertical stem.
SHIFT REGISTER UNIT, GATE LINE DRIVING DEVICE, AND DRIVING METHOD
A shift register unit, a gate line driving device includes multiple stages of the shift register units, and a driving method for being applied to the shift register unit; the shift register unit includes: an input module connected between an input terminal and a pull-up node, and configured to charge the pull-up node; an output module connected between the pull-up node, a first clock signal terminal and an output terminal, and configured to output to the output terminal a first clock signal received at the first clock signal terminal; a pull-up node reset module connected between a reset terminal, a pull-down node and the pull-up node, and configured to reset the pull-up node; and an output reset module connected between a second clock signal terminal, the pull-down node and the output terminal, and configured to reset the output terminal.