Patent classifications
G11B5/59616
Data storage drive with low-latency ports coupling multiple servo control processors
First and second servo control processors are coupled to respective first and second actuators that independently position first and second heads over one or more disks of a data storage drive. The first and second servo control processors are further coupled to first and second low-latency ports. First and second unidirectional buses couple the first and second low-latency ports. The first and second unidirectional busses are operable to isochronously exchange servo positioning data between the first and second servo control processors. The first and second servo control processors each use the servo positioning data to compensate for movement caused by another of the first and second servo control processors.
Primary and secondary servo timing gates used with simultaneously operating readers
First and second read channel logic circuits are configured to process first and second signals communicated from respective first and second readers that simultaneously read from a magnetic disk. A first servo detection circuit generates a primary servo gate based on timing data from the first reader. The primary servo gate is used for processing the first signal via the first read channel logic. A second servo detection circuit that generates a secondary servo gate based on the primary servo gate and an adjustment value. The secondary servo gate is used for processing the second signal via the second read channel logic.
Systems and methods for missed media sector alignment
A system includes a first sync mark detector circuit operable to apply a first sync mark detection algorithm to search a received media sector and overhead for a second sync mark after a failure to identify a first sync mark. A second sync mark detector circuit operable to apply a second sync mark detection algorithm to search the received media sector and overhead for the second sync mark. An anchor point identification circuit identifies an anchor point in the received media sector. A retry controller circuit causes a re-read of the received media sector and overhead when the first sync mark detector circuit fails to identify the first sync mark, and aligns the received media sector to yield an aligned media sector. A data processing circuit recovers an original user data set from the aligned media sector.
Systems and Methods for Missed Media Sector Alignment
Systems and methods relating generally to data processing, and more particularly to adjusting gain parameters in relation to data processing.
Systems and methods for synchronization hand shaking in a storage device
Systems, methods, devices, circuits for data processing, and more particularly to systems and methods for reporting a synchronization indication and for applying a synchronization window. As an example, a system is discussed that includes: a head assembly including a first read head and a second read head; a down track distance calculation circuit operable to calculate a down track distance between the first read head and the second read head; and a synchronization mark detection circuit. The synchronization mark detection circuit is operable to: assert a synchronization mark window based at a location based at least in part on the down track distance; query a first data set derived from the first read head for a synchronization mark occurring within the synchronization mark window; and query a second data set derived from the second read head for the synchronization mark occurring within the synchronization mark window.