Patent classifications
G11B20/1426
PHASE INTERPOLATOR
Apparatuses and methods for phase interpolators are provided. An example apparatus comprises a phase interpolator and a controller coupled to the phase interpolator. The controller is configured to provide a digital timing code to the phase interpolator, and the phase interpolator is configured to apply a correction to the received digital timing code based, at least in part, on phase interpolator error correction data from a data structure containing phase interpolator error correction data.
Partial reverse concatenation for data storage devices using composite codes
In one embodiment, a method includes writing data to a storage medium, via a write channel, by applying a partial reverse concatenated modulation code to the data prior to storing encoded data to the storage medium. The applying the partial reverse concatenated modulation code to the data includes application of a C2 encoding scheme to the data to produce C2-encoded data prior to application of one or more modulation encoding schemes to the C2-encoded data to produce modulated data, followed by application of a C1 encoding scheme to the modulated data subsequent to the application of the one or more modulation encoding schemes to produce the encoded data.
Phase interpolator
Apparatuses and methods for phase interpolators are provided. An example apparatus comprises a phase interpolator and a controller coupled to the phase interpolator. The controller is configured to provide a digital timing code to the phase interpolator, and the phase interpolator is configured to apply a correction to the received digital timing code based, at least in part, on phase interpolator error correction data from a data structure containing phase interpolator error correction data.
SIGNAL PROCESSING APPARATUS AND SIGNAL PROCESSING METHOD
There is provided a signal processing apparatus and a signal processing method capable of allowing data recorded at a high density to be robustly reproduced. A frame sync (FS) is restored by performing maximum likelihood decoding of the FS according to a time-varying trellis with a state and a state transition being limited according to a time, in maximum likelihood decoding of a reproduction signal reproduced from a disk-shaped recording medium, the FS representing a head of a frame, the FS of the frame being arranged at the head of the frame, the FS being recorded at the same positions in a track direction in two adjacent tracks.
DISK-TYPE RECORDING MEDIUM, RECORDING APPARATUS, RECORDING METHOD, REPRODUCING APPARATUS, AND REPRODUCING METHOD
There is provided a disk-type recording medium, a recording apparatus, a recording method, a reproducing apparatus, and a reproducing method, which are capable of recording, for example, data with high density and reproducing data recorded with high density robustly. In the disk-type recording medium, synchronization patterns for synchronization are recorded in two adjacent tracks with a shift in a track direction so that positions in the track direction do not overlap. The present technology can be applied to, for example, optical discs, other disk-type recording mediums, and the like.
Systems and methods for reading and decoding encoded data from a storage device
Systems and methods of reading data from a storage device are provided. A first codeword and a second codeword are read from a storage device, where the second codeword is positioned after the first codeword. The first and second codewords are decoded in parallel, and the decoding of the second codeword completes before the decoding of the first codeword completes. The decoded second codeword and a signal indicating whether the decoding of the second codeword is complete are transmitted to control circuitry before the decoding of the first codeword completes.
Log structured block device for hard disk drive
Example apparatus and methods provide a log structured block device for a hard disk drive (HDD). Data that is to be stored on an HDD is serialized and written as a series of data blocks using a sequential write. Information about where individual data blocks were supposed to be written (e.g., actual address, neighboring data blocks), where data blocks were actually written, and how often data blocks are accessed is maintained. During garbage collection, data blocks that are being accessed with similar frequencies may be relocated together, with the most frequently accessed (e.g., hottest) data blocks migrating to the outer cylinders of the disk and the least frequently accessed (e.g., coldest) data blocks migrating to the inner cylinders. Blocks stored in the same temperature regions that were intended to be located together when written may be repositioned to facilitate sequential reads.
PHASE INTERPOLATOR
Apparatuses and methods for phase interpolators are provided. An example apparatus comprises a phase interpolator and a controller coupled to the phase interpolator. The controller is configured to provide a digital timing code to the phase interpolator, and the phase interpolator is configured to apply a correction to the received digital timing code based, at least in part, on phase interpolator error correction data from a data structure containing phase interpolator error correction data.
Phase interpolator
Apparatuses and methods for phase interpolators are provided. An example apparatus comprises a phase interpolator and a controller coupled to the phase interpolator. The controller is configured to provide a digital timing code to the phase interpolator, and the phase interpolator is configured to apply a correction to the received digital timing code based, at least in part, on phase interpolator error correction data from a data structure containing phase interpolator error correction data.
System and method for line coding
A system and method for line coding of data. A serial transmitter includes a forward error correction encoding circuit followed by a bit conditioning circuit. The bit conditioning circuit counts the lengths of runs of consecutive identical digits and, when the count reaches a threshold, flips a bit. A serial receiver receives the data from the serial transmitter. The serial receiver includes a forward error correction decoding circuit, which re-flips bits flipped by the bit conditioning circuit of the serial transmitter.