Methods, systems, and devices for differential amplifier schemes for non-switching state compensation are described. During a read operation, a first node of a memory cell may be coupled with an input of differential amplifier while a second node of the memory cell may be biased with a first voltage (e.g., to apply a first read voltage across the memory cell). The second node of the memory cell may subsequently be biased with a second voltage (e.g., to apply a second read voltage across the memory cell), which may support the differential amplifier operating in a manner that compensates for a non-switching state of the memory cell. By compensating for a non-switching state of a memory cell during read operations, read margins may be increased.

A memory cell includes a thin film transistor over a semiconductor substrate. The thin film transistor comprising: a ferroelectric (FE) material contacting a word line, the FE material being a hafnium-comprising compound, and the hafnium-comprising compound comprising a rare earth metal; and an oxide semiconductor (OS) layer contacting a source line and a bit line, wherein the FE material is disposed between the OS layer and the word line.

Methods, systems, and devices for apparatus for differential memory cells are described. An apparatus may include a pair of memory cells comprising a first memory cell and a second memory cell, a word line coupled with the pair of memory cells and a plate line coupled with the pair of memory cells. The apparatus may further include a first digit line coupled with the first memory cell and a sense amplifier and a second digit line coupled with the second memory cell and the sense amplifier. The apparatus may include a select line configured to couple the first digit line and the second digit line with the sense amplifier.

Methods, systems, and devices for sensing techniques for differential memory cells are described. A method may include selecting a pair of memory cells that comprise a first memory cell coupled with a first digit line and a second memory cell coupled with a second digit line for a read operation, the pair of memory cells storing one bit of information. The method may further include applying a first voltage to a plate line coupled with the first memory cell and the second memory cell and applying a second voltage to a select line to couple the first digit line and the second digit line with a sense amplifier. The amplifier may sense a logic state of the pair of memory cells based on a difference between a third voltage of the first digit line and a fourth voltage of the second digit line.

The present disclosure includes apparatuses, methods, and systems for charge separation for memory sensing. An embodiment includes applying a sensing voltage to a memory cell, and determining a data state of the memory cell based, at least in part, on a comparison of an amount of charge discharged by the memory cell while the sensing voltage is being applied to the memory cell before a particular reference time and an amount of charge discharged by the memory cell while the sensing voltage is being applied to the memory cell after the particular reference time.

Methods, systems, and devices for cell data bulk reset are described. In some examples, a logic state (e.g., a first logic state) may be written to one or more memory cells based on an associated memory device transitioning power states. To write the first logic state to the memory cells, a first subset of digit lines may be driven to a first voltage and a plate may be driven to a second voltage. While the digit lines and plate are driven to the respective voltages, one or more word lines may be driven to the second voltage. In some instances, the word lines may be driven to the second voltage based on charge sharing occurring between adjacent word lines.

Methods, systems, and devices for programmable column access are described. A device may transfer voltages from memory cells of a row in a memory array to respective digit lines for the memory cells. The voltages may be indicative of logic values stored at the memory cells. The device may communicate respective control signals to a set of multiplexers coupled with the digit lines, where each multiplexer is coupled with a respective subset of the digit lines. Each multiplexer may couple a digit line of the respective subset of digit lines with a respective sense component for that multiplexer based on the respective control signal for that multiplexer.

A semiconductor memory device includes: memory units arranged in a first direction; first semiconductor layers arranged in the first direction and electrically connected to the memory units; first gate electrodes arranged in the first direction and opposed to the first semiconductor layers; a first wiring extending in the first direction and connected to the first semiconductor layers; second wirings arranged in the first direction, and connected to the first gate electrodes; second semiconductor layers arranged in the first direction and disposed at first end portions of the second wirings; second gate electrodes arranged in the first direction and opposed to the second semiconductor layers; third semiconductor layers arranged in the first direction and disposed at second end portions of the second wirings; and third gate electrodes arranged in the first direction and opposed to the third semiconductor layers.

The present disclosure relates to a memory device based on a ferroelectric capacitor, which includes a control unit for writing data into a memory cell or reading data from the memory cell and a plurality of memory cells arranged in an array; each memory cell includes an external interface, a first switch, a transistor, a first capacitor and a second capacitor, wherein at least one of the first capacitor and the second capacitor is a ferroelectric capacitor; the first switch has a first port connected with a first word line, a second port connected with a bit line, and a third port connected with one end of the first capacitor; and the transistor has a gate electrode connected with another end of the first capacitor and one end of the second capacitor, a source electrode connected with a first read terminal, and a drain electrode connected with a second read terminal, wherein another end of the second capacitor is connected with a second word line. According to the present disclosure, a polarized state of the ferroelectric capacitor in the memory cell is held or changed based on hysteresis characteristics of the ferroelectric capacitor, and the control unit is used to write data into or read data from the memory cell, which can implement non-destructive reading of data and longer endurance of a write operation.

A memory cell includes a transistor including a memory film extending along a word line; a channel layer extending along the memory film, wherein the memory film is between the channel layer and the word line; a source line extending along the memory film, wherein the memory film is between the source line and the word line; a first contact layer on the source line, wherein the first contact layer contacts the channel layer and the memory film; a bit line extending along the memory film, wherein the memory film is between the bit line and the word line; a second contact layer on the bit line, wherein the second contact layer contacts the channel layer and the memory film; and an isolation region between the source line and the bit line.