In some embodiments, an integrated circuit (IC) device includes an active semiconductor layer, a circuitry formed within the active semiconductor layer, a region including conductive layers formed above the active semiconductor layer, and a memory module formed in the region. The memory device includes a three-dimensional array of memory cells, each adapted to store a weight value, and adapted to generate at each memory cell a signal indicative of a product between the stored weight value and an input signal applied to the memory cell. The memory module is further adapted to transmit the product signals from the memory cell simultaneously in the direction of the active semiconductor layer.

Methods, systems, and devices for sense timing coordination are described. In some systems, to sense the logic states of memory cells, a memory device may generate an activation signal and route the activation signal over a signal line (e.g., a dummy word line) located at a memory array level of the memory device to one or more sense amplifiers. Based on receiving the activation signal, a sense amplifier may latch and determine the logic state of a corresponding memory cell. A first sense amplifier may sense a state of a first memory cell at a first time and a second sense amplifier may sense a state of a second memory cell at a second time in response to the same activation signal due to a propagation delay of the activation signal routed over the signal line (e.g., and corresponding to a propagation delay for activating a word line).

In some embodiments, the present disclosure relates to a memory device, including a plurality of content addressable memory (CAM) units arranged in rows and columns and configured to store a plurality of data states, respectively. A CAM unit of the plurality of CAM units includes a first ferroelectric memory element, a plurality of word lines extending along the rows and configured to provide a search query to the plurality of CAM units for bitwise comparison between the search query and the data states of the plurality of CAM units, and a plurality of match lines extending along the columns and configured to output a plurality of match signals, respectively from respective columns of CAM units. A match signal of a column is asserted when the data states of the respective CAM units of the column match corresponding bits of the search query.

A semiconductor device comprises a first conductive structure extending along a vertical direction and a second conductive structure extending along the vertical direction. The second conductive structure is spaced apart from the first conductive structure along a lateral direction. The semiconductor device further comprises a plurality of third conductive structures each extending along the lateral direction. The plurality of third conductive structures are disposed across the first and second conductive structures. The first and second conductive structures each have a varying width along the lateral direction. The plurality of third conductive structures are configured to be applied with respective different voltages in accordance with the varying width of the first and second conductive structures.

Methods, systems, and devices for apparatus for differential memory cells are described. An apparatus may include a pair of memory cells comprising a first memory cell and a second memory cell, a word line coupled with the pair of memory cells and a plate line coupled with the pair of memory cells. The apparatus may further include a first digit line coupled with the first memory cell and a sense amplifier and a second digit line coupled with the second memory cell and the sense amplifier. The apparatus may include a select line configured to couple the first digit line and the second digit line with the sense amplifier.

Disclosed is a memory device which includes a plurality of memory banks and control logic. The control logic receives a plurality of column address bits and a plurality of read commands. The control logic includes a processing-in-memory (PIM) address generator. In a first operation mode, the control logic sends the plurality of column address bits to a memory bank. In a second operation mode, when the PIM address generator receives a first read command of the plurality of read commands, the control logic sends, to the memory bank, a first PIM address generated based on remaining column address bits other than some column address bits of the plurality of column address bits.

Methods, systems, and devices for ferroelectric memory plate power reduction are described. A plate line may be coupled with a voltage source, a capacitor, and one or more sections of a bank of ferroelectric memory cells. During a write operation, the capacitor may be discharged onto the plate line and the resulting voltage may be adjusted (e.g., increased) by the voltage source before writing one or more memory cells. During a write-back operation, a capacitor associated with one or more memory cells may be discharged onto the plate line and stored at the capacitor. The charge may be re-applied to the plate line and adjusted (e.g., increased) by the voltage source during the write-back.

In an embodiment, a device includes: a first word line over a substrate, the first word line including a first conductive material; a first bit line intersecting the first word line; a first memory film between the first bit line and the first word line; and a first conductive spacer between the first memory film and the first word line, the first conductive spacer including a second conductive material, the second conductive material having a different work function than the first conductive material, the first conductive material having a lower resistivity than the second conductive material.

Dual-precision analog memory cells and arrays are provided. In some embodiments, a memory cell, comprises a non-volatile memory element having an input terminal and at least one output terminal; and a volatile memory element having a plurality of input terminals and an output terminal, wherein the output terminal of the volatile memory element is coupled to the input terminal of the non-volatile memory element, and wherein the volatile memory element comprises: a first transistor coupled between a first supply and a common node, and a second transistor coupled between a second supply and the common node; wherein the common node is coupled to the output terminal of the volatile memory element; and wherein gates of the first and second transistors are coupled to respective ones of the plurality of input terminals of the volatile memory element.

Memory devices and methods of operating memory devices in which maintenance operations can be scheduled on an as-needed basis for those memory portions where activity (e.g., operations in excess of a predetermined threshold) warrants a maintenance operation are disclosed. In one embodiment, an apparatus comprises a memory including a memory location, and circuitry configured to determine a count corresponding to a number of operations at the memory location, to schedule a maintenance operation for the memory location in response to the count exceeding a first predetermined threshold, and to decrease the count by an amount corresponding to the first predetermined threshold in response to executing the scheduled maintenance operation. The circuitry may be further configured to disallow, in response to determining that the count has reached a maximum permitted value, further operations at the memory location until after the count has been decreased.