A semiconductor device including a substrate; a stack including electrodes and a channel separation pattern, the electrodes being stacked on the substrate and spaced apart from each other, and the channel separation pattern being between adjacent electrodes; and a vertical structure penetrating the stack, wherein the vertical structure includes a conductive pillar, a channel structure, and an interposing layer between the conductive pillar and the channel structure, the channel structure includes first and second channel layers vertically spaced apart from each other by the channel separation pattern, the electrodes include first and second electrodes, which are connected to the first and second channel layers, the channel separation pattern is between the first channel layer and the second channel layer, and the channel separation pattern is between one second electrode that is connected to the first channel layer and one first electrode that is connected to the second channel layer.

Systems and methods for detecting the presence of a body in a network without fiducial elements, using signal absorption, and signal forward and reflected backscatter of radio frequency (RF) waves caused by the presence of a biological mass in a communications network.

Methods, systems, and apparatuses for storing operational information related to operation of a non-volatile array are described. For example, the operational information may be stored in a in a subarray of a memory array for use in analyzing errors in the operation of memory array. In some examples, an array driver may be located between a command decoder and a memory array. The array driver may receive a signal pattern used to execute an access instruction for accessing non-volatile memory cells of a memory array and may access the first set of non-volatile memory cells according to the signal pattern. The array driver may also store the access instruction (e.g., the binary representation of the access instruction) at a non-volatile subarray of the memory array.

An example IC device includes a memory cell having a vertical transistor that includes an opening in an insulator material, where sidewall(s) and the bottom of the opening are lined with a channel material and a gate insulator material. The lined opening is at least partially filled with a gate electrode material so that the gate insulator material is between the channel material and the gate electrode material. The IC device further includes a first control line for the memory cell (e.g., a wordline) coupled to the gate electrode material, and a second control line for the memory cell (e.g., a bitline or a plateline) at least partially wrapping around the sidewall of the opening to electrically couple to the channel material at the sidewall. The vertical transistor may be a hysteretic transistor and/or may be further coupled to a hysteretic capacitor.

Three-dimensional ferroelectric memory cell architectures are discussed related to improved memory cell performance and density. Such three-dimensional ferroelectric memory cell architectures include groups of vertically stacked transistors accessed by vertical bit lines and horizontal word lines. Groups of such stacks of transistors are arrayed laterally. Adjacent transistor stacks are separated by isolation material or memory structures inclusive of capacitor structures or plate line structures.

Techniques herein may allow a row of a subarray in a bank of a memory device to be activated before a precharge operation has been completed for a previously opened row of memory cells in the same bank. Each subarray within the bank may be associated with a respective local latching circuit, which may be used to maintain phases at the subarray independent of subsequent commands to the same bank. For example, the latching circuit may internalize timing signals triggered by a precharge command for a first row such that if an activation command is received for a different subarray in the same bank at a time before the precharge operation of the first row is complete, the precharge operation may continue until the first row is closed, as the timing signals triggered by the precharge command may be maintained locally at the subarray using the latching circuit.

Methods, systems, and devices for an arbitrated sense amplifier are described. A memory device may couple a memory cell to a first node via a digit line and may couple the first node to a second node. If a voltage at the second node is associated with a first logic value stored at the memory cell, the memory device may couple the second node with a third node and may charge the third node according to the voltage. However, if the voltage at the second node is associated with a second logic value stored at the memory cell, the memory device may not couple the second node with the third node. The memory device may compare the resulting voltage at the third node with a reference voltage and may generate a signal indicative of a logic value stored by the memory cell.

A method of writing data to a Ferroelectric-FET (FeFET) based non-volatile memory device can be provided by applying a voltage pulse at a write voltage level with a write polarity at a gate electrode of a FeFET device with reference to a source electrode of the FeFET device, as a write operation to the FeFET device to establish a state for the FeFET device, changing the voltage pulse, directly after the write operation, to a non-zero bias voltage level with a bias polarity that is opposite to the write polarity, at the gate electrode with reference to the source electrode for a delay time to reduce neutralization of a trap state associated with the write operation of the FeFET device, and changing the voltage pulse, after the delay time, to a read voltage level as a read operation to the FeFET device to determine the state of the FeFET device established during the write operation.

Disclosed is a threshold voltage-programmable field effect transistor-based (e.g., a ferro-electric field effect transistor (FeFET)-based) memory circuit employing source-line and/or bit-line-applied variable programming assist voltages. For single-bit data storage in a FeFET, decremental programming assist voltages are selectively applied by a voltage driver to the source-line and/or the bit-line connected to a FeFET during repeat programming processes when previous attempts at programming have failed. For multi-bit data storage in a FeFET, different programming assist voltages are associated with different multi-bit data values and at least one specific programming assist voltage is applied by a voltage driver to the source-line and/or the bit-line connected to a selected FeFET during a programming process to achieve storage of a specific multi-bit data value. Optionally, multiple FeFETs in the same row can be currently programmed with different multi-bit data values. Optionally, different decremental programming assist voltages are applied if/when repeat programming processes are required.

Various embodiments of the present application are directed a memory layout for reduced line loading. In some embodiments, a memory device comprises an array of bit cells, a first conductive line, a second conductive line, and a plurality of conductive bridges. The first and second conductive lines may, for example, be source lines or some other conductive lines. The array of bit cells comprises a plurality of rows and a plurality of columns, and the plurality of columns comprise a first column and a second column. The first conductive line extends along the first column and is electrically coupled to bit cells in the first column. The second conductive line extends along the second column and is electrically coupled to bit cells in the second column. The conductive bridges extend from the first conductive line to the second conductive line and electrically couple the first and second conductive lines together.