A memory cell includes a node and first transistor to third transistors. The third transistor and the second transistor are electrically connected to a fourth wiring and a third wiring in series, respectively. A gate of the third transistor is electrically connected to a second wiring. A gate of the second transistor is electrically connected to the node. In the first transistor, a gate is electrically connected to a first wiring, one of a source and a drain is electrically connected to the fourth wiring, and the other of the source and the drain is electrically connected to the node. The first transistor includes an oxide semiconductor layer where a channel is formed and a channel length and a channel width thereof are each shorter than 100 nm. A maximum potential of the first wiring is lower than or equal to 2 V.

A memory cell includes a node and first transistor to third transistors. The third transistor and the second transistor are electrically connected to a fourth wiring and a third wiring in series, respectively. A gate of the third transistor is electrically connected to a second wiring. A gate of the second transistor is electrically connected to the node. In the first transistor, a gate is electrically connected to a first wiring, one of a source and a drain is electrically connected to the fourth wiring, and the other of the source and the drain is electrically connected to the node. The first transistor includes an oxide semiconductor layer where a channel is formed and a channel length and a channel width thereof are each shorter than 100 nm. A maximum potential of the first wiring is lower than or equal to 2 V.

Some embodiments include an integrated assembly having a primary access transistor. The primary access transistor has a first source/drain region and a second source/drain region. The first and second source/drain regions are coupled to one another when the primary access transistor is in an ON mode, and are not coupled to one another when the primary access transistor is in an OFF mode. A charge-storage device is coupled with the first source/drain region. A digit line is coupled with the second source/drain region through a secondary access device. The secondary access device has an ON mode and an OFF mode. The digit line is coupled with the charge-storage device only when both the primary access transistor and the secondary access device are in their respective ON modes.

Described herein are two transistor (2T) memory cells that use TFTs as access and gain transistors. When one or both transistors of a 2T memory cell are implemented as TFTs, these transistors may be provided in different layers above a substrate, enabling a stacked architecture. An example 2T memory cell includes an access TFT provided in a first layer over a substrate, and a gain TFT provided in a second layer over the substrate, the first layer being between the substrate and the second layer (i.e., the gain TFT is stacked in a layer above the access TFT). Stacked TFT based 2T memory cells allow increasing density of memory cells in a memory array having a given footprint area, or, conversely, reducing the footprint area of the memory array with a given memory cell density.

Described herein are two transistor (2T) memory cells that use TFTs as access and gain transistors. When one or both transistors of a 2T memory cell are implemented as TFTs, these transistors may be provided in different layers above a substrate, enabling a stacked architecture. An example 2T memory cell includes an access TFT provided in a first layer over a substrate, and a gain TFT provided in a second layer over the substrate, the first layer being between the substrate and the second layer (i.e., the gain TFT is stacked in a layer above the access TFT). Stacked TFT based 2T memory cells allow increasing density of memory cells in a memory array having a given footprint area, or, conversely, reducing the footprint area of the memory array with a given memory cell density.

A capacitive synaptic component consisting of a layered structure composed of a gate electrode, having a first dielectric layer connected to the gate electrode, a second dielectric layer and a readout electrode connected to the second dielectric layer, and an intermediate layer arranged between the first dielectric layer and the second dielectric layer. A method for writing and reading the component is also disclosed. The component addresses a high capacitive deviation ratio without changing the plate spacing, the surface area or the relative permittivity or limiting the lateral scalability by the intermediate layer having adjustable shielding behaviour in an electric field, proceeding from the gate electrode towards the readout electrode, and the intermediate layer having one or more suitable contacts that produce a charge flow into or a charge flow out of the intermediate layer.

A memory device includes an address generation circuit, an address processing circuit and a refresh control circuit. The address generation circuit generates a first intermediate address according to a row address. The first intermediate address includes a first wordline address and an identification code indicating whether a first wordline indicated by the first wordline address is a normal or redundant wordline. The address processing circuit refers to the first intermediate address to generate a second intermediate address indicating a second wordline adjacent to the first wordline. The second intermediate address includes a second wordline address and an identification code indicating whether the second wordline is a normal or redundant wordline. The refresh control circuit determines a disturbance count of the second wordline each time the first wordline is activated, and refers to the disturbance count to determine whether to output the second wordline address to refresh the second wordline.

A memory device includes an address generation circuit, an address processing circuit and a refresh control circuit. The address generation circuit generates a first intermediate address according to a row address. The first intermediate address includes a first wordline address and an identification code indicating whether a first wordline indicated by the first wordline address is a normal or redundant wordline. The address processing circuit refers to the first intermediate address to generate a second intermediate address indicating a second wordline adjacent to the first wordline. The second intermediate address includes a second wordline address and an identification code indicating whether the second wordline is a normal or redundant wordline. The refresh control circuit determines a disturbance count of the second wordline each time the first wordline is activated, and refers to the disturbance count to determine whether to output the second wordline address to refresh the second wordline.

A gain cell includes a write bit line input, a read bit line output, a write trigger input and a read trigger input. The write element writes a data level from the write bit line input to the gain cell when triggered by the write trigger input. The retention element buffers between an internal buffer node and an internal storage node during data retention. The retention element also connects or disconnects the buffer node to a first constant voltage according to the data level being retained in the gain cell. The read element decouples the storage node from the read bit line output during data read. The read element also connects and disconnects the read bit line output to a second constant voltage according to the data level being read from the gain cell.

A gain cell includes a write bit line input, a read bit line output, a write trigger input and a read trigger input. The write element writes a data level from the write bit line input to the gain cell when triggered by the write trigger input. The retention element buffers between an internal buffer node and an internal storage node during data retention. The retention element also connects or disconnects the buffer node to a first constant voltage according to the data level being retained in the gain cell. The read element decouples the storage node from the read bit line output during data read. The read element also connects and disconnects the read bit line output to a second constant voltage according to the data level being read from the gain cell.