An information processing apparatus includes a detection unit and first and second classification units. The detection unit detects an event which causes a state of at least one bank constituting dynamic random access memory (DRAM) to transition. The first classification unit classifies the at least one bank state based on the detected event. The second classification unit classifies a DRAM state based on the at least one bank state. Statistical information that is based on the at least one bank or DRAM state is displayed with respect to a predetermined unit time. The at least one bank state and the DRAM state each includes at least one of the following: an operating state, in which data is being transferred, an inoperative state, in which data transfer is not possible due to a predetermined constraint, or a pause state, in which, although there is no constraint, data is not being transferred.

An electronic device includes a command generation circuit configured to generate a refresh command and a driving control signal, which are enabled during an all-bank refresh operation, according to a logic level combination of an internal chip selection signal and an internal command address. The electronic device also includes a buffer control circuit configured to generate, from the refresh command and the driving control signal, a first buffer enable signal for enabling a first group of buffers and a second buffer enable signal for enabling a second group of buffers.

A memory performs a sequence of ECS operations to read a codeword, detect and correct any errors, and write the corrected codeword back to the memory array. An ECS circuit counts errors which are detected, and sets a value of one or more ECS registers in a mode register if the count exceeds a threshold filter at the end of the ECS cycle. The memory also includes a forced ECS readout circuit, which responsive to a command, for example from a controller, sets the value(s) in the ECS register(s).

Embodiments of the present application provide a method and apparatus for determining a refresh counter of a DRAM. The method includes: writing data to a target memory cell connected with a target word line in the DRAM, and controlling the DRAM to perform refreshes starting from a preset word line according to a preset rule; determining, according to whether the data can be read accurately from the target memory cell after the refreshes, an intermediate refresh counter of refreshes on the target word line; and controlling, based on the intermediate refresh counter, the DRAM to perform refreshes starting from the target word line according to the preset rule, and determining the refresh counter of the DRAM according to whether the data can be read accurately from the target memory cell after the refreshes.

Embodiments of the present application provide a method and apparatus for determining a refresh counter of a DRAM. The method includes: writing data to a target memory cell connected with a target word line in the DRAM, and controlling the DRAM to perform refreshes starting from a preset word line according to a preset rule; determining, according to whether the data can be read accurately from the target memory cell after the refreshes, an intermediate refresh counter of refreshes on the target word line; and controlling, based on the intermediate refresh counter, the DRAM to perform refreshes starting from the target word line according to the preset rule, and determining the refresh counter of the DRAM according to whether the data can be read accurately from the target memory cell after the refreshes.

Apparatuses, systems, and methods for refresh address masking. A memory device may refresh word lines as part of refresh operation by cycling through the word lines in a sequence. However, it may be desirable to avoid activating certain word lines (e.g., because they are defective). Refresh masking logic for each bank may include a fuse latch which stores a selected address associated with a word line to avoid. When a refresh address is generated it may be compared to the selected address. If there is a match, a refresh stop signal may be activated, which may prevent refreshing of the word line(s).

A semiconductor memory, a refresh method and an electronic device are provided. The semiconductor memory includes a main storage area and a mark storage area, multiple storage rows are arranged in the main storage area, and multiple first flag bits are arranged in the mark storage area. Each storage row has a correspondence with one first flag bit, and the first flag bit is used for indicating whether the storage row is an aggressor row of a row hammer event.

A semiconductor memory, a refresh method and an electronic device are provided. The semiconductor memory includes a main storage area and a mark storage area, multiple storage rows are arranged in the main storage area, and multiple first flag bits are arranged in the mark storage area. Each storage row has a correspondence with one first flag bit, and the first flag bit is used for indicating whether the storage row is an aggressor row of a row hammer event.

The present embodiments provide a system that supports self-refreshing operations in a memory device. During operation, the system transitions the memory device from an auto-refresh state, wherein a memory controller controls refreshing operations for the memory device, to a self-refresh state, wherein the memory device controls the refreshing operations. While the memory device is in the self-refresh state, the system sends progress information for the refreshing operations from the memory device to the memory controller. Next, upon returning from the self-refresh state to the auto-refresh state, the system uses the progress information received from the memory device to control the sequencing of subsequent operations by the memory controller.

The present embodiments provide a system that supports self-refreshing operations in a memory device. During operation, the system transitions the memory device from an auto-refresh state, wherein a memory controller controls refreshing operations for the memory device, to a self-refresh state, wherein the memory device controls the refreshing operations. While the memory device is in the self-refresh state, the system sends progress information for the refreshing operations from the memory device to the memory controller. Next, upon returning from the self-refresh state to the auto-refresh state, the system uses the progress information received from the memory device to control the sequencing of subsequent operations by the memory controller.