A pseudo-triple-port memory is provided with read datapaths and write datapaths. The pseudo-triple-port memory includes a plurality of pseudo-triple-port bitcells, each pseudo-triple-port first bitcell having a first read port coupled to a first bit line, a second read port coupled to a second bit line, and a write port coupled to the first bit line and to the second bit line.

A pseudo-triple-port memory is provided with read datapaths and write datapaths. The pseudo-triple-port memory includes a plurality of pseudo-triple-port bitcells, each pseudo-triple-port first bitcell having a first read port coupled to a first bit line, a second read port coupled to a second bit line, and a write port coupled to the first bit line and to the second bit line.

A compute cell for in-memory multiplication of a digital data input and a balanced ternary weight, and an in-memory computing device including an array of the compute cells, are provided. In one aspect, the compute cell includes a set of input connectors for receiving modulated input signals representative of a sign and a magnitude of the data input, and a memory unit configured to store the ternary weight. A logic unit connected to the set of input connectors and the memory unit receives the data input and the ternary weight. The logic unit selectively enables one of a plurality of conductive paths for supplying a partial charge to a read bit line during a compound duty cycle of the set of input signals as a function of the respective signs of data input and ternary weight, and disables each of the plurality of conductive paths if at least one of the ternary weight and data input have zero magnitude.

A compute cell for in-memory multiplication of a digital data input and a balanced ternary weight, and an in-memory computing device including an array of the compute cells, are provided. In one aspect, the compute cell includes a set of input connectors for receiving modulated input signals representative of a sign and a magnitude of the data input, and a memory unit configured to store the ternary weight. A logic unit connected to the set of input connectors and the memory unit receives the data input and the ternary weight. The logic unit selectively enables one of a plurality of conductive paths for supplying a partial charge to a read bit line during a compound duty cycle of the set of input signals as a function of the respective signs of data input and ternary weight, and disables each of the plurality of conductive paths if at least one of the ternary weight and data input have zero magnitude.

A singled ended current sense amplifier circuit including an input stage having a bitline node, a sense node and a feedback circuit comprising a feedback inverter configured to provide an amplified voltage from the bitline node. The feedback inverter may include first and second NMOS transistors serially connected to a feedback node and first and second PMOS transistors serially connected to the feedback node. The feedback circuit may include a third NMOS transistor having a gate terminal connected to the feedback node and a drain terminal connected to the sense node. The input stage may include a third PMOS transistor operating as a current source to generate a sense current which flows in a current sensing path between the sense node and the bitline node. The input stage may act as a regulator to keep the voltage at the bitline node constant.

A singled ended current sense amplifier circuit including an input stage having a bitline node, a sense node and a feedback circuit comprising a feedback inverter configured to provide an amplified voltage from the bitline node. The feedback inverter may include first and second NMOS transistors serially connected to a feedback node and first and second PMOS transistors serially connected to the feedback node. The feedback circuit may include a third NMOS transistor having a gate terminal connected to the feedback node and a drain terminal connected to the sense node. The input stage may include a third PMOS transistor operating as a current source to generate a sense current which flows in a current sensing path between the sense node and the bitline node. The input stage may act as a regulator to keep the voltage at the bitline node constant.

Certain aspects provide an apparatus for signal processing in a neural network. The apparatus generally includes a first set of computation in memory (CIM) cells configured as a first kernel for a neural network computation, the first set of CIM cells comprising on one or more first columns and a first plurality of rows of a CIM array, and a second set of CIM cells configured as a second kernel for the neural network computation, the second set of CIM cells comprising on one or more second columns and a second plurality of rows of the CIM array. In some aspects, the one or more first columns are different than the one or more second columns, and the first plurality of rows are different than the second plurality of rows.

Certain aspects provide an apparatus for signal processing in a neural network. The apparatus generally includes a first set of computation in memory (CIM) cells configured as a first kernel for a neural network computation, the first set of CIM cells comprising on one or more first columns and a first plurality of rows of a CIM array, and a second set of CIM cells configured as a second kernel for the neural network computation, the second set of CIM cells comprising on one or more second columns and a second plurality of rows of the CIM array. In some aspects, the one or more first columns are different than the one or more second columns, and the first plurality of rows are different than the second plurality of rows.

A digital micromirror device includes a plurality of micromirror cells on a semiconductor die. Each respective cell includes a memory circuit and an electrode selection circuit. At least some of the micromirror cells include a micromirror and each respective memory circuit controls a micromirror tilt angle. For a given memory circuit controlled to a first tilt angle, a measurement circuit measures a first value indicative of a capacitance between a first electrode and the micromirror and measures a second value indicative of a capacitance on the second electrode. For a second micromirror tilt angle, the measurement circuit measures a third value indicative of a capacitance between the first electrode and the micromirror and measures a fourth value indicative of a capacitance on the second electrode. The measurement circuit generates a signal indicative of whether the micromirror is stuck at a particular angle or missing.

A digital micromirror device includes a plurality of micromirror cells on a semiconductor die. Each respective cell includes a memory circuit and an electrode selection circuit. At least some of the micromirror cells include a micromirror and each respective memory circuit controls a micromirror tilt angle. For a given memory circuit controlled to a first tilt angle, a measurement circuit measures a first value indicative of a capacitance between a first electrode and the micromirror and measures a second value indicative of a capacitance on the second electrode. For a second micromirror tilt angle, the measurement circuit measures a third value indicative of a capacitance between the first electrode and the micromirror and measures a fourth value indicative of a capacitance on the second electrode. The measurement circuit generates a signal indicative of whether the micromirror is stuck at a particular angle or missing.