Methods, systems, and devices for a differential write operation are described. The operations described herein may be used to alter a portion of a program file from a first state to a second state. For example, a file (e.g., a patch file) that is associated with a signature may be received at a memory device. Based on an authentication process, the file may be used to alter the program file to the second state. In some examples, the program file may be altered to the second state using a buffer of the memory device. A host system may transmit a file that includes the difference between the first state and the second state. A signature may be associated with the file and may be used to authenticate the file.

Methods, systems, and devices for a differential write operation are described. The operations described herein may be used to alter a portion of a program file from a first state to a second state. For example, a file (e.g., a patch file) that is associated with a signature may be received at a memory device. Based on an authentication process, the file may be used to alter the program file to the second state. In some examples, the program file may be altered to the second state using a buffer of the memory device. A host system may transmit a file that includes the difference between the first state and the second state. A signature may be associated with the file and may be used to authenticate the file.

An integrated circuit device that has improved write margin at low operating voltages is disclosed. The integrated circuit device can include an SRAM array that has end power select circuits that can include selection circuits that provide a controllable impedance path between a power supply potential and an array power line. A power supply detection circuit may provide an assist enable signal when a power supply potential is low enough that write assist is needed. A power control circuit may provide end power control signals to end power select circuits to selectively control an impedance path between a power supply potential and an array power line to provide an I-R drop to a selected memory cell. In this way, write margins may be improved at low operating voltages.

A circuit includes a memory array, a control circuit configured to identify an address of a first row containing a weak cell, and store corresponding address information in a storage device, and an address decoding circuit including NAND pairs, inverter pairs, and a logic tree. Each NAND pair receives corresponding bits of the address information and the address of the first row and corresponding inverted bits of the address information and the address of the first row inverted by corresponding inverter pairs, and output terminals of the NAND pairs are connected to the logic tree. The logic tree matches the address information with the address of the first row based on output logic levels from the NAND pairs and, in response to the corresponding address information matching the address of the first row, activates a second row of the memory array simultaneously with the first row being activated.

Embodiments of three-dimensional (3D) memory devices with a 3D NAND memory array having a plurality of pages, an on-die cache coupled to the memory array on a same chip and configured to cache a plurality of batches of program data between a host and the memory array, the on-die cache having SRAM cells, and a controller coupled to the on-die cache on the same chip. The controller is configured to check a status of an (N−2).sup.th batch of program data, N being an integer equal to or greater than 2, program an (N−1).sup.th batch of program data into respective pages in the 3D NAND memory array, and cache an N.sup.th batch of program data in respective space in the on-die cache as a backup copy of the N.sup.th batch of program data.

A method includes determining, via status polling at a first interval, an indicator of an almost ready status of a set of memory cells of a memory device, based on the indicator of the almost ready status, determining the set of memory cells of the memory device is almost ready to complete execution of an operation on the set of memory cells of the memory device, and responsive to determining the set of memory cells of the memory device is almost ready to complete execution of the operation, performing status polling at a second interval.

A memory system includes a plurality of first memory units, a plurality of read word lines, and a plurality of read bit lines. Each first memory unit of the plurality of first memory units includes a second memory unit, a first transistor coupled to the second memory unit, and a second transistor coupled to the second memory unit and the first transistor. Each read word line of the plurality of read word lines is coupled to a plurality of first transistors disposed along a corresponding row. Each read bit line of the plurality of read bit lines is coupled to a plurality of second transistors disposed along a corresponding column.

A memory system includes a plurality of first memory units, a plurality of read word lines, and a plurality of read bit lines. Each first memory unit of the plurality of first memory units includes a second memory unit, a first transistor coupled to the second memory unit, and a second transistor coupled to the second memory unit and the first transistor. Each read word line of the plurality of read word lines is coupled to a plurality of first transistors disposed along a corresponding row. Each read bit line of the plurality of read bit lines is coupled to a plurality of second transistors disposed along a corresponding column.

A ternary content addressable memory (TCAM) semiconductor device includes a first and second data storage portions each connected to a bit line. The first data storage portion is connected to a first word line, and to a first and third group of in series transistors. The second data storage portion is connected to a second word line, and to a second and fourth group of in series transistors. The first group and second group of in series transistors are each connected to a first match line. The first group is connected to a first search line bar, and the second group is connected to a first search line. A third and fourth group of in series transistors are each connected to a second match line. The third group is connected to a second search line, and the fourth group is connected to a second search line bar.

A method includes determining, via status polling at a first interval, an indicator of an almost ready status of a set of memory cells of a memory device, based on the indicator of the almost ready status, determining the set of memory cells of the memory device is almost ready to complete execution of an operation on the set of memory cells of the memory device, and responsive to determining the set of memory cells of the memory device is almost ready to complete execution of the operation, performing status polling at a second interval.