A memory system includes a non-volatile memory having a plurality of memory cells, and a controller configured to carry out write operations in a first mode in which n-bit data is written per target memory cell of the non-volatile memory until an allowable data amount of data items has been written, and then, in a second mode in which m-bit data is written per target memory cell of the non-volatile memory, where n is an integer of one or more and m is an integer greater than n. The controller is further configured to detect that an idle state, in which a command has not been received from the host, has continued for a threshold period of time or more, increase the allowable data amount in response thereto, and after the increase, carry out a write operation to write data items in the non-volatile memory in the first mode.

A controller controls a semiconductor memory device including a plurality of memory blocks. The controller may include a controller control unit and a storing unit. The controller control unit compares the number of times of a read of an original memory block among the plurality of memory blocks with a predetermined copy generation reference value, determines whether to generate copy data of original data stored in the original memory block, and generates a command corresponding to the determination. The storage unit stores the copy generation reference value and address information about the original memory block.

Endurance mechanisms are introduced for memories such as non-volatile memories for broad usage including caches, last-level cache(s), embedded memory, embedded cache, scratchpads, main memory, and storage devices. Here, non-volatile memories (NVMs) include magnetic random-access memory (MRAM), resistive RAM (ReRAM), ferroelectric RAM (FeRAM), phase-change memory (PCM), etc. In some cases, features of endurance mechanisms (e.g., randomizing mechanisms) are applicable to volatile memories such as static random-access memory (SRAM), and dynamic random-access memory (DRAM). The endurance mechanisms include a wear leveling scheme that uses index rotation, outlier compensation to handle weak bits, and random swap injection to mitigate wear out attacks.

A data storage apparatus includes a controller configured to control data input to and output from a storage according to a request transmitted from a host apparatus, a buffer memory configured to store data transmitted and received between the host apparatus and the storage, and the storage including a plurality of memory cells and a verification component configured to verify a state of a target memory cell before write data is programmed in the target memory cell while the write data is transmitted from the host apparatus in response to a write request of the host apparatus.

A method and apparatus for updating data in a memory for electrical compensation, the method comprises: when a master chip receives a power-off signal, writing a serial number of a block being updated or a predetermined value into a nonvolatile memory. In the apparatus, only a nonvolatile memory is required to be provided external to a master chip to store the serial number of the block (the sequence of the block) being updated currently during power-off. Upon a next power-on, it is determined that which rows have their data lost during the previous power-off according to the serial number of the block, and then data of adjacent rows is used to replace the data of the rows which have their data lost during the previous power-off; therefore, the operation is simple and the efficiency is high, so that the time for updating the data is short, without affecting the memory's lifespan.

Various examples are directed to memory systems comprising a component and a processing device. The memory system may comprise a plurality of blocks. A first portion of the plurality of blocks may be retired and a second portion of the plurality of blocks may be unretired. The processing device receives a sanitize operation for the plurality of blocks. The processing device initiates a first erase cycle at a first retired block of the plurality of blocks. The processing device determines that the first erase cycle was not successful and sets an erase indicator to false.

A memory system includes a non-volatile memory having a plurality of memory cells, and a controller configured to carry out write operations in a first mode in which n-bit data is written per target memory cell of the non-volatile memory until an allowable data amount of data items has been written, and then, in a second mode in which m-bit data is written per target memory cell of the non-volatile memory, where n is an integer of one or more and m is an integer greater than n. The controller is further configured to detect that an idle state, in which a command has not been received from the host, has continued for a threshold period of time or more, increase the allowable data amount in response thereto, and after the increase, carry out a write operation to write data items in the non-volatile memory in the first mode.

Systems, methods, and/or devices are used to manage open blocks within non-volatile storage devices, in order to improve the reliability of non-volatile storage devices. In some embodiments, when a shut-down request is received from a host device, the storage device fetches information about open blocks and their boundary regions susceptible to data reliability issues, and for each identified boundary region, the storage device programs a region contiguous to the identified boundary region. In some embodiments, the device updates an XOR parity table used for XOR parity management with the information that the region contiguous to the identified boundary is programmed. Subsequently, in some embodiments, the storage device can use the information, stored in the contiguous region and/or the XOR parity table, for data recovery in the event of a data loss. As a result, the reliability of the non-volatile storage device is improved.

Various examples are directed to memory systems comprising a component and a processing device. The memory system may comprise a plurality of blocks. A first portion of the plurality of blocks may be retired and a second portion of the plurality of blocks may be unretired. The processing device receives a sanitize operation for the plurality of blocks. The processing device initiates a first erase cycle at a first retired block of the plurality of blocks. The processing device determines that the first erase cycle was not successful and sets an erase indicator to false.

A byte-programming method for programming data from a page register to a non-volatile memory array includes reading data of a selected byte in the page register and programming the data to the memory cells of the non-volatile memory corresponding to a selected column address; determining whether to update an array column address according to the selected column address, which includes: determining whether the data of the selected byte matches specified content; when the data of the selected byte matches the specified content, not updating the array column address; and when the data of the selected byte does not match the specified content, updating the array column address according to the selected column address; and determining whether the selected column address is the last column address.