A data storage device can detect for a failure in decoding of an x-bit row address and/or a y-bit column of an (x+y)-bit address. The data storage device decodes the x-bit row address and/or the y-bit column address to provide wordlines (WLs) and/or bitlines (BLs) to access one or more cells from among a memory array of the data storage device. The data storage device compares one or more subsets of the WLs and/or of the BLs to each other to detect for the failure. The data storage device determines the failure is present in the decoding of the x-bit row address and/or the y-bit column of the (x+y)-bit address when one or more WL and/or BL from among the one or more subsets of the WLs and/or the BLs differ.

A semiconductor memory device includes a memory array including a plurality of memory blocks, an address allocation information storage unit which stores address allocation information, a block selection circuit which selects one memory block which corresponds to an input address which is input on the basis of the address allocation information and a refresh control circuit which controls a refreshing operation. One of the memory blocks is allotted to a surplus memory block. The refresh control circuit transfers data which is stored in one memory block which is a refreshing object to the surplus memory block and thereafter allocates address information of the memory block which was the refreshing object to the surplus memory block to which the data is transferred and newly allots the memory block which was the refreshing object to the surplus memory block.

According to one embodiment, a semiconductor device includes a non-volatile memory, a temperature measurement circuit that measures a temperature of the non-volatile memory, and a controller. The controller also writes information about the temperature which is measured by the temperature measurement circuit in the non-volatile memory together when writing data in the non-volatile memory. Further, the controller performs write-back processing of writing data, which is written at a temperature in a rewriting temperature range, back when the temperature measured by the temperature measurement circuit is not in the rewriting temperature range.

A memory device includes a plurality of memory cells arranged in series in a semiconductor body. First and second dummy memory cells arranged in series between a first string select switch and a first edge memory cell at a first end of the plurality of memory cells. The first dummy memory cell is adjacent the first edge memory cell, and the second dummy memory cell is adjacent the first string select switch. A channel line includes channels for the plurality of memory cells and the first and second dummy memory cells. Control circuitry is adapted for programming a selected memory cell in the plurality of memory cells corresponding to a selected word line by applying a switching voltage to the first dummy memory cell, the switching voltage having a first voltage level during a first time interval, and thereafter changing to a second voltage level higher than the first voltage level.

Various embodiments are related to non-volatile memories, systems, and methods of using such. Some instances provide a computer readable medium that includes instructions executable by one or more processors of an NVM controller for controlling a NVM using memory pages where the NVM controller having a predefined error correction coding, ECC, capability (ECCCTRL). Executing the instructions may cause the NVM controller to: perform a monitoring process and perform a transitioning process.

A memory device includes a plurality of memory cells arranged in series in a semiconductor body. First and second dummy memory cells arranged in series between a first string select switch and a first edge memory cell at a first end of the plurality of memory cells. The first dummy memory cell is adjacent the first edge memory cell, and the second dummy memory cell is adjacent the first string select switch. A channel line includes channels for the plurality of memory cells and the first and second dummy memory cells. Control circuitry is adapted for programming a selected memory cell in the plurality of memory cells corresponding to a selected word line by applying a switching voltage to the first dummy memory cell, the switching voltage having a first voltage level during a first time interval, and thereafter changing to a second voltage level higher than the first voltage level.

According to one embodiment, a memory system includes a semiconductor memory including a memory cell, and a controller configured to control the semiconductor memory and capable of creating second data based on first data read from the memory cell. Upon receiving a physical erase request for the first data held in the memory cell from an external device, the controller transmits one of an erase instruction and a write instruction for the second data to the semiconductor memory.

A method for writing and reading data in memory cells, comprising, when writing a data in a block of a first memory zone, a step consisting of writing in a second memory zone a temporary information structure metadata comprising a start flag, an identifier of the temporary information structure, an information about the location of the block in the first memory zone, and a final flag, and, after a power on of the first memory zone, searching for an anomaly in temporary information structures present in the second memory zone.

A non-volatile storage apparatus includes a set of non-volatile memory cells and one or more control circuits in communication with the set of non-volatile memory cells. The one or more control circuits are configured to identify a most recently written portion of the set of non-volatile memory cells and to compare an error rate of data stored in the most recently written portion with a reference error rate from a reference portion of the set of non-volatile memory cells to determine whether the most recently written portion is fully written or partially written.

A memory management method, a memory control circuit unit and a memory storage device are provided. The method includes: performing a single-layer erasing operation on one of physical erasing units; performing a multi-layer erasing operation on another one of the physical erasing units; and performing a wear leveling operation based on the one and the another one of the physical erasing units, wherein the another one of the physical erasing units is performed the wear leveling operation first than the one of the physical erasing units.