Disclosed in some examples are systems, methods, memory devices, and machine readable mediums for a fast secure data destruction for NAND memory devices that renders data in a memory cell unreadable. Instead of going through all the erase phases, the memory device may remove sensitive data by performing only the pre-programming phase of the erase process. Thus, the NAND doesn't perform the second and third phases of the erase process. This is much faster and results in data that cannot be reconstructed. In some examples, because the erase pulse is not actually applied and because this is simply a programming operation, data may be rendered unreadable at a per-page level rather than a per-block level as in traditional erases.

Provided herein may be a memory device and a method of operating the memory device. The memory device may include: a memory block including a plurality of normal memory cells and a plurality of dummy memory cells; a peripheral circuit configured to perform an erase operation and a soft program operation on the memory block; and control logic configured to control the peripheral circuit to control the erase operation and the soft program operation, wherein during the soft program operation, threshold voltages of first dummy memory cells of the plurality of dummy memory cells are controlled to be higher than threshold voltages of second dummy memory cells of the plurality of dummy memory cells.

A storage device comprising: a nonvolatile memory device including a plurality of memory blocks; and a device controller configured to control the nonvolatile memory device to determine a memory block to perform a refresh operation and to control the memory block to perform the refresh operation to recover data of the memory block.

Numerous embodiments of programming systems and methods for use with a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. Selected cells thereby can be programmed with extreme precision to hold one of N different values.

A storage device comprising: a nonvolatile memory device including a plurality of memory blocks; and a device controller configured to control the nonvolatile memory device to determine a memory block to perform a refresh operation and to control the memory block to perform the refresh operation to recover data of the memory block.

Disclosed is a method for automatically recovering data of an electronically erasable programmable read only memory (EEPROM) storing configuration information of a slave device by a programmable logic controller (PLC) communication module using an EtherCAT network when the data of the EEPROM is modified or incorrect.

A semiconductor memory device according to an embodiment includes a string, a bit line, a well line, and a sequencer. The string includes first and second select transistors, and memory cell transistors using a ferroelectric material. The bit line and the well line are connected to the first and second select transistors, respectively. At a time in an erase verify operation, the sequencer is configured to apply a first voltage to the memory cell transistors, to apply a second voltage lower than the first voltage to the first select transistor, to apply a third voltage lower than the first voltage to the second select transistor, to apply a fourth voltage to the bit line, and to apply a fifth voltage higher than the fourth voltage to the well line.

A memory device and an operating method of the memory device is disclosed. The memory device includes a memory cell array including a plurality of memory blocks. The memory device further includes a peripheral circuit for performing an erase voltage application operation, a first erase verify operation, and a second erase verify operation on a selected memory block among the plurality of memory blocks. The memory device also includes a control logic for setting a start erase voltage of an erase operation, based on a result of the first erase verify operation, and controlling the peripheral circuit to perform the second erase verify operation when it is determined that the first erase verify operation on the selected memory block has been passed.

A method for an erase operation on a nonvolatile memory array with low-latency erase suspend is described. The nonvolatile memory array includes a plurality of blocks of memory cells, each block including a plurality of sectors of memory cells. The method includes, in response to an erase command identifying a block in the plurality of blocks in the array, erasing the plurality of sectors in the identified block, and determining whether there are over-erased cells in each sector. The method includes recording the over-erased cells for the sector. The method also includes responsive to suspend before a soft program pulse for the sector, applying a correction pulse to the recorded cells.

A storage device with a charge trapping (CT) based memory may include improved data retention performance. Data retention problems, such as charge loss in CT memory may increase for a particular programmed state when a neighboring state is at erased state. Modifying the erase state with post write erase conditioning (PWEC) by pushing up deeply erased states can reduce the lateral charge movement and improve high temperature data retention. In particular, the erase state may be reprogrammed such that the erase distribution is tighter with a higher voltage.