A nonvolatile semiconductor memory device includes a control circuit configured to control a soft program operation of setting nonvolatile memory cells to a first threshold voltage distribution state of the nonvolatile memory cells. When a characteristic of the nonvolatile memory cells is in a first state, the control circuit executes the soft program operation by applying a first voltage for setting the nonvolatile memory cells to the first threshold voltage distribution state to first word lines, and applying a second voltage higher than the first voltage to a second word line. When the characteristic of the nonvolatile memory cells is in a second state, the control circuit executes the soft program operation by applying a third voltage equal to or lower than the first voltage to the first word lines and applying a fourth voltage lower than the second voltage to the second word line.

A nonvolatile semiconductor memory device includes a control circuit configured to control a soft program operation of setting nonvolatile memory cells to a first threshold voltage distribution state of the nonvolatile memory cells. When a characteristic of the nonvolatile memory cells is in a first state, the control circuit executes the soft program operation by applying a first voltage for setting the nonvolatile memory cells to the first threshold voltage distribution state to first word lines, and applying a second voltage higher than the first voltage to a second word line. When the characteristic of the nonvolatile memory cells is in a second state, the control circuit executes the soft program operation by applying a third voltage equal to or lower than the first voltage to the first word lines and applying a fourth voltage lower than the second voltage to the second word line.

A method of operating a memory controller, the memory controller configured to control a nonvolatile memory device, the nonvolatile memory device including a plurality of memory blocks. The method including detecting an invalid block among the plurality of memory blocks; determining an invalid pattern based on a state of the invalid block; and performing an operation on the invalid block such that the invalid block has the invalid pattern.

An embodiment of a semiconductor package apparatus may include technology to attempt to program data in a first portion of a nonvolatile memory, determine if the attempt was successful, and recover the data to a second portion of the nonvolatile memory with an internal data move operation if the attempt is determined to be not successful. Other embodiments are disclosed and claimed.

Circuit designs and operating techniques for a storage device that includes, in one implementation, a memory controller configured to control a memory device including a plurality of memory blocks, each including a plurality of memory cells. The memory controller may include a memory device interface configured to perform data communication with the memory device, and a soft program controller communicatively coupled to the memory device interface and configured to count a number of times that an erase operation on an erase target memory block, among the plurality of memory blocks, has been suspended until the erase operation is completed, and to perform a soft program operation on the erase target memory block after the erase operation has been completed, based on the number of iterations that the erase operation on the erase target memory block has been suspended.

A semiconductor memory device and a method of operating the same are provided. The method of operating the semiconductor memory device includes determining a target word line coupled to an over-programmed memory cell, backing up data stored in memory cells coupled to the target word line in a second memory area, wherein the se second memory area is different from a first memory area where the memory cells coupled to the target word line are disposed, and applying a stepped-up read pass voltage to the target word line when a read operation is performed on a selected memory cell in a memory block coupled to the target word line, wherein the selected memory cell is different from the over-programmed memory cell. Therefore, the operation reliability of the semiconductor memory device is improved.

A nonvolatile semiconductor memory device includes a control circuit configured to control a soft program operation of setting nonvolatile memory cells to a first threshold voltage distribution state of the nonvolatile memory cells. When a characteristic of the nonvolatile memory cells is in a first state, the control circuit executes the soft program operation by applying a first voltage for setting the nonvolatile memory cells to the first threshold voltage distribution state to first word lines, and applying a second voltage higher than the first voltage to a second word line. When the characteristic of the nonvolatile memory cells is in a second state, the control circuit executes the soft program operation by applying a third voltage equal to or lower than the first voltage to the first word lines and applying a fourth voltage lower than the second voltage to the second word line.

According to one embodiment, a memory system includes a non-volatile semiconductor memory that includes a memory cell and a controller having a memory storing a write parameter used in a write operation to the memory cell. The controller instructs the non-volatile semiconductor memory to perform the write operation to the memory cell using the write parameter, receives, from the non-volatile semiconductor memory, a result of checking of the write parameter which is obtained in the write operation and updates the write parameter stored in the memory on the basis of the result of checking of the write parameter.

A nonvolatile semiconductor memory device includes a control circuit configured to control a soft program operation of setting nonvolatile memory cells to a first threshold voltage distribution state of the nonvolatile memory cells. When a characteristic of the nonvolatile memory cells is in a first state, the control circuit executes the soft program operation by applying a first voltage for setting the nonvolatile memory cells to the first threshold voltage distribution state to first word lines, and applying a second voltage higher than the first voltage to a second word line. When the characteristic of the nonvolatile memory cells is in a second state, the control circuit executes the soft program operation by applying a third voltage equal to or lower than the first voltage to the first word lines and applying a fourth voltage lower than the second voltage to the second word line.

A non-volatile memory device may include a memory cell array, a peripheral circuit and a control logic. The memory cell array may include pages including data cells and over-program flag cells configured to represent whether or not the data cells may correspond to an over-programmed cells. The peripheral circuit may be configured to store data in the memory cell array or read the data from the memory cell array. The control logic may be configured to determine whether or not the data cells are programmable when a program command may be received from an external device. The control logic may be configured to program the over-program flag cell corresponding to the data cells when the data cells are not programmable.