A controller for controlling a memory device comprising a plurality of multi-level cell memory blocks, the controller includes: a processor suitable for controlling the memory device to perform a read operation on a target logical page using some of the plurality of read voltages in a selected read voltage set; and an error correction code (ECC) component suitable for determining whether the read operation is successful, by performing error detection and correction on data generated in the read operation and output from the memory device, wherein, when the read operation is determined to be successful, the processor updates the selected read voltage set with the read voltages used in the read operation when it is successful and estimated values of unused read voltages of the selected read voltage set, the estimated values being determined based on the used read voltages.

The present disclosure is directed to read sample offset most probable bit operation associated with a memory component. A processing device generates a first set of read data associated with a memory component, the first set of read data comprising a first sequence of bit values. The processing device generates a second set of read data associated with the memory component, the second set of read data comprising a second sequence of bit values. The processing device generates a third set of read data associated with the memory component, the third set of read data comprising a third sequence of bit values. A most probable bit operation is performed to compare the first sequence of bit values, the second sequence of bit values, and the third sequence of bit values to generate and store a most probable bit sequence.

A memory system includes a memory device including a memory device including a plurality of blocks, each block having a plurality of pages to store data; and a controller suitable for selecting specific memory blocks among the plurality memory blocks, acquiring error bit information of the plurality of pages in each of the specific memory blocks, generating a memory block group management list of each of the specific memory blocks to classify the specific memory blocks into different memory block groups or a same memory block group based on the error bit information, and performing a test read operation on the plurality of pages in each of the plurality of memory blocks based on whether the specific memory blocks are classified into different memory block groups or the same memory block group.

A flash memory storage apparatus includes a memory cell array and a voltage generating circuit. The memory cell array includes at least one memory cell string coupled between a bit line and a source line and including memory cells; each memory cell is coupled to a corresponding word line. The voltage generating circuit is coupled to the memory cell array and configured to output a bias voltage to the word line. A first voltage is applied to a selected word line. A second voltage and a third voltage are applied to unselected second and third word lines, respectively. The first voltage is greater than the second voltage, and the second voltage is greater than the third voltage. The second word line and the third word line are located on two sides of the first word line. A biasing method of a flash memory storage apparatus is also provided.

A method for measuring interference in a memory device is provided. The method includes: programming a selected memory cell among a plurality of memory cells connected in series between a bit line and a source line; measuring a first noise value of the programmed selected memory cell; programming an adjacent memory cell adjacent to the selected memory cell among the plurality of memory cells; measuring a second noise value of the selected memory cell, after the programming of the adjacent memory cell is completed; and determining interference on the selected memory cell based on the first noise value and the second noise value. The first noise value and the second noise value are measured by detecting a low frequency noise of a cell current of the selected memory cell.

A control method for a multi-channel non-volatile memory is shown. When reading a read target on the non-volatile memory, the controller increases the read count of the monitored unit to which the read target belongs and, based on the read count, determines whether to move data of the monitored unit covering the read target to a safe space to deal with reading interference. The monitored unit is smaller than a cross-channel management unit in read-count group. The controller accesses a parallel accessing space of the non-volatile memory in parallel through all of the channels, and allocates the parallel accessing space based on the cross-channel management unit.

A computer-implemented method, according to one approach, is for calibrating read voltages associated with a block of memory having more than one word-line therein. The computer-implemented method includes: for each of the word-lines in the block: calculating an absolute shift value for a reference read voltage associated with the given word-line. A relative shift value is also determined for each of the remaining read voltages associated with the given word-line, and the relative shift values are determined with respect to the reference read voltage. Moreover, each of the read voltages associated with the given word-line are adjusted using the absolute shift value and each of the respective relative shift values.

The present disclosure is directed to read sample offset most probable bit operation associated with a memory component. A processing device performs a first read, a second read, and a third read of data from the memory component using a center value corresponding to a read threshold voltage value, a negative offset value, and a positive offset value, respectively. The processing device performs a most probable bit operation on the first set of data, the second set of data, and the third set of data to generate a most probable bit sequence corresponding to the data associated with the memory component. The processing device can store or output the generated most probable bit sequence.

A measure associated with a characteristic of a die of a memory device is obtained. It is determined whether the measure satisfies a first criterion to group one or more die into a first die family. If it is determined that the measure satisfies the first criterion, the die is associated with the first die family.

Reduction of program disturb degradation in a flash memory cell array is facilitated by selectively switching wordline voltage levels in a sequence that reduces the likelihood of trapping electrons in memory cell channels. During a program verify operation for a memory cell in a memory cell string, a flash memory system switches wordline voltage levels from high-to-low for interface wordlines, prior to switching wordline voltages from high-to-low for other wordlines in a memory cell string. Selectively switching wordlines in a sequence in the memory cell string enables electrons to migrate to ground or to a source voltage through upper and lower select gates.