Provided herein may be a memory controller and a method of operating the same. The memory controller may include a read operation controller configured to provide a read command to a memory device and receive read data corresponding to the read command, a read fail determiner configured to determine, based on the read data, whether a read operation has passed or failed, and to generate read information including a result of the read operation and information about performance of the read operation and a read fail processor configured to select, based on the read information, one of a read retry operation, among a plurality of read retry operations, to be performed on the selected page and an operation of setting a control time for a bit line coupled to the selected page, and to control the memory device to perform the selected operation.

A memory system includes a nonvolatile memory configured to execute one of a plurality of read operations, including a first read operation and a second read operation, and a memory controller configured to issue a read command to the nonvolatile memory to cause the nonvolatile memory to execute one of the plurality of read operations. The memory controller is configured to receive a read request, estimate a reliability level of a result of a read operation to be executed by the nonvolatile memory to read data from a physical address specified in the read request, select one of the first and second read operations to be executed first in a read sequence corresponding to the read request by the nonvolatile memory based on the estimated reliability level, and instruct the nonvolatile memory to execute the selected read operation.

Error recovery operations are provided for a memory system. The memory system includes a memory device including a plurality of cells and a controller. The controller performs a read on a select cell among the plurality of cells. The controller adjusts a log-likelihood ratio (LLR) value on the select cell to generate an adjusted LLR value, based on first read data on the select cell and second read data on at least one neighbor cell adjacent to the select cell, when the read on the select cell fails.

A storage device includes a nonvolatile memory device including a memory block and a memory controller. The memory block includes a first memory region connected with a first word line and a second memory region connected with a second word line. The memory controller sets a read block voltage based on a first read voltage of the first memory region. The memory controller determines a second read voltage of the second memory region based on variation information and the read block voltage.

A computer-implemented method, according to one approach, is for calibrating read voltages associated with a block of memory having more than one word-line therein. The computer-implemented method includes: for each of the word-lines in the block: calculating an absolute shift value for a reference read voltage associated with the given word-line. A relative shift value is also determined for each of the remaining read voltages associated with the given word-line, and the relative shift values are determined with respect to the reference read voltage. Moreover, each of the read voltages associated with the given word-line are adjusted using the absolute shift value and each of the respective relative shift values.

A memory system includes a memory device including a plurality of memory blocks, each block having a plurality of pages to store data; and a controller suitable for detecting a number of error bits from data stored in the plurality of pages; summing the number of error bits; generating a bad word line list based on the sum of the error bits; and performing a test read operation on the plurality of pages based on the bad word line list.

A computer-implemented method, according to one approach, includes: using a first calibration scheme to calibrate the given page in the block by calculating a first number of independent read voltage offset values for the given page. An attempt is made to read the calibrated given page, and in response to determining that an error correction code failure occurred when attempting to read the calibrated given page, a second calibration scheme is used to recalibrate the given page in the block. The second calibration scheme is configured to calculate a second number of independent read voltage offset values for the given page. An attempt to read the recalibrated given page is also made. In response to determining that an error correction code failure did occur when attempting to read the recalibrated given page, one or more instructions to relocate data stored in the given page are sent.

A memory management method and a storage controller are provided. The method includes performing a decoding operation to a first data stored in a first word line among multiple word lines of a rewritable non-volatile memory module to determine whether the decoding operation is successful or failed, and obtain a first error value of the first word line; when the decoding operation is determined as successful, determining whether to mark the first word line as a bad word line according to the first error value and a first threshold; and when the decoding operation is determined as failed, obtaining a second error value of a second word line adjacent to the first word line, and determining whether to mark both of the first and second word lines as the bad word line according to the first error value, the second error value, and a first threshold.

A computer-implemented method, according to one approach, is for calibrating read voltages for a block of memory. The computer-implemented method includes: determining a current operating state of a block which includes more than one word-line therein, and where more than one read voltage is associated with each of the word-lines. Moreover, for each of the word-lines in the block: one of the read voltages associated with the given word-line is selected as a reference read voltage, and an absolute shift value is calculated for the reference read voltage. A relative shift value is determined for each of the remaining read voltages associated with the given word-line, where the relative shift values are determined with respect to the reference read voltage. Furthermore, each of the read voltages associated with the given word-line are adjusted using the absolute shift value and each of the respective relative shift values.

A nonvolatile memory device includes a nonvolatile memory cell including a first cell transistor and a second cell transistor electrically coupled to a bit line in parallel and configured to respectively have a first physical size and a second physical size, a cell transistor selector coupled between the nonvolatile memory cell and a ground voltage terminal to control electrical connections between the first cell transistor and the ground voltage terminal, and between the second cell transistor and the ground voltage terminal, and a read voltage selection circuit suitable for selectively supplying one of a first read voltage and a second read voltage to the bit line.