NOR memory strings may be used for implementations of logic functions involving many Boolean variables, or to generate analog signals whose magnitudes are each representative of the bit values of many Boolean variables. The advantage of using NOR memory strings in these manners is that the logic function or analog signal generation may be accomplished within one simultaneous read operation on the NOR memory strings.

A 3-dimensional array of NOR memory strings being organized by planes of NOR memory strings, in which (i) the storage transistors in the NOR memory strings situated in a first group of planes are configured to be programmed, erased, program-inhibited or read in parallel, and (ii) the storage transistors in NOR memory strings situated within a second group of planes are configured for storing resource management data relating to data stored in the storage transistors of the NOR memory strings situated within the first group of planes, wherein the storage transistors in NOR memory strings in the second group of planes are configured into sets.

A method to perform an on demand refresh operation of a memory sub-system is disclosed. The method includes identifying a temporal attribute of user data stored in the memory component, upon determining that the identified temporal attribute satisfies a time condition, providing an indication whether a refresh operation of the user data improves performance of the memory component, receiving an indication to perform the refresh operation of the memory component, and responsive to a time between the refresh operation and a previously performed refresh operation not satisfying a threshold criterion, refraining from performing the refresh operation of the memory component.

A processing device of a memory sub-system is configured to perform a plurality of write operations on a memory device comprising a plurality of memory units; responsive to performing each write operation on a respective first memory unit of the memory device, the processing device is configured to identify a candidate memory unit that has been written to by a at least a threshold fraction of the plurality of write operations performed on the memory device; determine whether a threshold refresh criterion is satisfied; and responsive to determining that the threshold refresh criterion is satisfied, refresh data stored at one or more of the memory units that are proximate to the candidate memory unit.

A method for programming a non-volatile memory structure, comprises initiating a two-dimensional fractional number of bits-per-cell programming scheme of a plurality of memory cells, wherein the memory structure comprises: (1) a first memory array comprising a first population of memory cells and the associated peripheral circuitry disposed below the first population of cells, (2) a second memory array positioned above the first memory array and comprising a second population of memory cells and associated peripheral circuitry disposed above the second population of cells, and (3) a data bus tap electrically coupling the first and second memory arrays. Further, the method comprises: (1) storing input data in data latches associated with the first array and with the second array. Additionally, the method comprises converting the stored data using data conversion logic implemented by a data path circuit of the first and second arrays and rewriting the converted data to the latches.

A memory system includes a plurality of blocks of memory blocks, each including a plurality of memory cells. The method for programming the memory system includes during a program process, performing a first program operation to program a first memory block, waiting for a delay time after the first program operation is completed, after waiting for the delay time, performing an all-level threshold voltage test to determine if threshold voltages of the first memory block are greater than corresponding threshold voltages, and performing a second program operation to program the first memory block according to a result of the all-level threshold voltage test.

An apparatus includes one or more control circuits configured to connect to a plurality of non-volatile memory cells through a plurality of word lines. The one or more control circuits are configured to, for each target word line of a plurality of target word lines to be read, select either a first neighboring word line or a second neighboring word line as a selected neighboring word line according to whether non-volatile memory cells of the first neighboring word line are in an erased condition. The one or more control circuits are further configured to determine a read voltage to read non-volatile memory cells of a corresponding target word line according to an amount of charge in non-volatile memory cells of the selected neighboring word line.

A non-volatile memory device includes a plurality of wordlines, each comprising a plurality of cells, a hard decode configured to read each cell of the plurality of cells at a hard decode voltage, a left read sense configured to read voltage values of each cell to the left of the hard decode voltage at a left read sense voltage, a right read sense configured to read voltage values of each cell to the right of the hard decode voltage at a right read sense voltage, a first combiner configured to determine a difference of voltage values read by the left read sense and right read sense to produce a dispersion signal, and a second combiner configured to determine a sum of the voltage values read by the left read sense and right read sense to produce a deviation signal.

A semiconductor device includes a memory circuit, an error correction code circuit, a register circuit and a write circuit. The memory circuit is configured to output, in response to at least one address signal, first data associated with at least one memory cell in the memory circuit. The error correction code circuit is configured to convert the first data to second data and configured to generate error information when the first data is not identical to the second data. The register circuit is configured to output, based on the error information, reset information corresponding to the at least one address signal. The write circuit is configured to reset the at least one memory cell according to the reset information. A method is also disclosed herein.

A memory includes an upper deck and a lower deck. The upper deck includes a first upper dummy word line. The lower deck includes a first lower dummy word line. A method for reducing program disturbance of the memory includes adjusting a first upper bias voltage applied to the first upper dummy word line and/or a first upper threshold voltage of the first upper dummy word line to adjust a first difference between the first upper bias voltage and the first upper threshold voltage; and adjusting a first lower bias voltage applied to the first lower dummy word line and/or a first lower threshold voltage of the first lower dummy word line to adjust a second difference between the first lower bias voltage and the first lower threshold voltage.