A semiconductor memory device includes first conductive layers arranged in a first direction, second conductive layers arranged in the first direction, a first semiconductor layer disposed therebetween, a charge storage layer, a first wiring electrically connected to the first semiconductor layer, and first and second transistors connected to the first and the second conductive layers. In the semiconductor memory device, in an erase operation, a first voltage is supplied to at least a part of the first conductive layers, an erase voltage larger than the first voltage is supplied to the first wiring, and a first signal voltage is supplied to at least a part of the second transistors. The first signal voltage turns OFF the second transistor.

Provided herein may be a memory system and a method of operating the same. The memory system may include a memory device configured to include a plurality of memory blocks and copy data from victim blocks among the plurality of memory blocks into a target memory block during a garbage collection operation, and a memory controller configured to control the memory device to perform the garbage collection operation, and configured to control the memory device, during the garbage collection operation, to erase the data stored in the victim blocks using a multi-erase method.

A method for erasing non-volatile memory including applying a first voltage pulse to a non-volatile memory cell to perform a first erase operation of the non-volatile memory cell and determining that a threshold voltage of the non-volatile memory cell is greater than a test voltage. The method further comprising updating a dedicated memory location with a value; and checking the non-volatile memory cell to determine whether the threshold voltage of the non-volatile memory cell is less than an erase-verify voltage to verify that the first erase operation has been performed successfully.

According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a control unit. The memory cell array includes a plurality of memory cells arranged in a matrix. The control unit erases data of the memory cells. The control unit interrupts the erase operation of the memory cells and holds an erase condition before the interrupt in accordance with a first command during the erase operation, and resumes the erase operation based on the held erase condition in accordance with a second command.

A method of programming data into a memory device including an array of memory cells is disclosed. The method comprises receiving at least one program command that addresses a number of the memory cells for a programming operation to program data in the memory cells. The at least one program command is executed by iteratively carrying out at least one program/verify cycle to incrementally program the addressed memory cells with the program data. A secondary command may be selectively received after initiating but before completing the programming operation. The programming operation may be selectively resumed by first verifying the memory cells, then carrying out at least one program/verify cycle.

According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a control unit. The memory cell array includes a plurality of memory cells arranged in a matrix. The control unit erases data of the memory cells. The control unit interrupts the erase operation of the memory cells and holds an erase condition before the interrupt in accordance with a first command during the erase operation, and resumes the erase operation based on the held erase condition in accordance with a second command.

A nonvolatile memory device includes a memory cell array including first to fourth planes, a page buffer circuit that includes first to fourth page buffer units connected with the first to fourth planes, respectively, an input/output circuit that includes a first input/output unit connected with the first to fourth page buffer units and a second input/output unit connected with the second and fourth page buffer units, and control logic that controls the input/output circuit to output first data from one of the first to fourth page buffer units through the first input/output unit in a first read mode and output second data from one of the first and third page buffer units through the first input/output unit and third data from one of the second and fourth page buffer units through the second input/output unit in a second read mode.

A data arranging method, a memory control circuit unit and a memory storage device for flash memory are provided. The method can be applied to a flash memory with a three-dimensional (3D) structure, an embedded memory device, or a solid-state hard disk. The method includes: writing at least one piece of data to at least one second physical erasing unit of at least one first physical erasing unit, and obtaining a distribution state of valid data in a plurality of physical erasing units; adjusting a specific threshold value according to the distribution state; and when the number of the at least one first physical erasing unit is less than the specific threshold value, performing a valid data merging operation.

A data arranging method, a memory control circuit unit and a memory storage device for flash memory are provided. The method can be applied to a flash memory with a three-dimensional (3D) structure, an embedded memory device, or a solid-state hard disk. The method includes: writing at least one piece of data to at least one second physical erasing unit of at least one first physical erasing unit, and obtaining a distribution state of valid data in a plurality of physical erasing units; adjusting a specific threshold value according to the distribution state; and when the number of the at least one first physical erasing unit is less than the specific threshold value, performing a valid data merging operation.

A memory device includes a plurality of memory blocks and each memory block includes a plurality of columns of memory cells. Each column of memory cells is coupled to a corresponding bit line. Upon completion of a power-up sequence, detect if a current leakage of corresponding columns in a group of memory blocks is greater than a predetermined level. If the current leakage of the corresponding columns in the group of memory blocks is greater than the predetermined level, perform an over-erasure correction on the corresponding columns.