Provided herein may be a memory system and a method of operating the same. The memory system may include a memory device configured to include a plurality of memory blocks and copy data from victim blocks among the plurality of memory blocks into a target memory block during a garbage collection operation, and a memory controller configured to control the memory device to perform the garbage collection operation, and configured to control the memory device, during the garbage collection operation, to erase the data stored in the victim blocks using a multi-erase method.

A memory device, including a plurality of planes, includes a mode setting component to set an operation mode of the memory device as a verify pass mode to allow a verify operation, performed in the plurality of planes, to forcibly pass; and a verify signal generator for outputting a verify pass signal signaling that the verify operation has passed for each of the plurality of planes.

A nonvolatile semiconductor memory device includes a control circuit configured to control a soft program operation of setting nonvolatile memory cells to a first threshold voltage distribution state of the nonvolatile memory cells. When a characteristic of the nonvolatile memory cells is in a first state, the control circuit executes the soft program operation by applying a first voltage for setting the nonvolatile memory cells to the first threshold voltage distribution state to first word lines, and applying a second voltage higher than the first voltage to a second word line. When the characteristic of the nonvolatile memory cells is in a second state, the control circuit executes the soft program operation by applying a third voltage equal to or lower than the first voltage to the first word lines and applying a fourth voltage lower than the second voltage to the second word line.

A non-volatile storage apparatus includes a plurality of non-volatile memory cells and control circuitry. The control circuitry is configured to apply one or more soft erase pulses to the plurality of non-volatile memory cells to reduce threshold voltages of the plurality of non-volatile memory cells from initial levels corresponding to programmed data to intermediate levels below the initial levels and above an erased level. The control circuitry is configured to apply one or more soft programming pulse to increase threshold voltages of the plurality of non-volatile memory cells from the intermediate levels to final levels corresponding to the programmed data.

A non-volatile storage system comprises a group of non-volatile memory cells, and one or more control circuits in communication with the group. The one or more control circuits are configured to perform a plurality of passes to revise a read reference signal based on comparisons of numbers of non-volatile memory cells in the group having a value for a physical property (e.g., threshold voltage or resistance) in adjacent regions. With each pass the adjacent regions are smaller. The one or more control circuits are configured to establish a final read reference signal based on a signal associated with one of the adjacent regions on a final pass of the plurality of passes. The one or more control circuits are configured to use the final read reference signal to distinguish between two adjacent data states stored in the group.

A non-volatile storage system comprises a group of non-volatile memory cells, and one or more control circuits in communication with the group. The one or more control circuits are configured to perform a plurality of passes to revise a read reference signal based on comparisons of numbers of non-volatile memory cells in the group having a value for a physical property (e.g., threshold voltage or resistance) in adjacent regions. With each pass the adjacent regions are smaller. The one or more control circuits are configured to establish a final read reference signal based on a signal associated with one of the adjacent regions on a final pass of the plurality of passes. The one or more control circuits are configured to use the final read reference signal to distinguish between two adjacent data states stored in the group.

A non-volatile storage apparatus includes a plurality of non-volatile memory cells and control circuitry. The control circuitry is configured to apply one or more soft erase pulses to the plurality of non-volatile memory cells to reduce threshold voltages of the plurality of non-volatile memory cells from initial levels corresponding to programmed data to intermediate levels below the initial levels and above an erased level. The control circuitry is configured to apply one or more soft programming pulse to increase threshold voltages of the plurality of non-volatile memory cells from the intermediate levels to final levels corresponding to the programmed data.

A non-volatile storage system comprises a group of non-volatile memory cells, and one or more control circuits in communication with the group. The one or more control circuits are configured to perform a plurality of passes to revise a read reference signal based on comparisons of numbers of non-volatile memory cells in the group having a value for a physical property (e.g., threshold voltage or resistance) in adjacent regions. With each pass the adjacent regions are smaller. The one or more control circuits are configured to establish a final read reference signal based on a signal associated with one of the adjacent regions on a final pass of the plurality of passes. The one or more control circuits are configured to use the final read reference signal to distinguish between two adjacent data states stored in the group.

A non-volatile storage system comprises a group of non-volatile memory cells, and one or more control circuits in communication with the group. The one or more control circuits are configured to perform a plurality of passes to revise a read reference signal based on comparisons of numbers of non-volatile memory cells in the group having a value for a physical property (e.g., threshold voltage or resistance) in adjacent regions. With each pass the adjacent regions are smaller. The one or more control circuits are configured to establish a final read reference signal based on a signal associated with one of the adjacent regions on a final pass of the plurality of passes. The one or more control circuits are configured to use the final read reference signal to distinguish between two adjacent data states stored in the group.

A data erasure device is for a non-volatile semiconductor memory device, which includes cells in which data is written by an application of a first voltage and erased by an application of a second voltage differing from the first voltage. The data erasure device includes a controller. The controller applies a second voltage to the cells over first time period with multiple occurrences to set the cells into a first erasure state, and applies the second voltage to the cells over second time period, which is longer than the first time period, to set the cells in a second erasure state deeper than the first erasure state. The controller changes a number of occurrences of applying the second voltage over the first time period to each of the cells or each of multiple cell groups having the cells according to respective erasure states of the cells.