Methods, systems and apparatus including computer-readable mediums for partially erasing blocks in a memory system to increase reliability are provided. In one aspect, a memory system includes a memory having a plurality of blocks and a memory controller coupled to the memory. The memory controller is configured to: execute a first erase operation on a particular block in the memory, the particular block including multiple sub-blocks each having respective memory cells, one or more memory cells in the particular block being in one or more programmed states before the first erase operation, then execute a second erase operation on a first sub-block of the particular block such that first respective memory cells of the first sub-block are in an erased state after the second erase operation. The memory controller can be configured to not execute the second erase operation on the one or more other sub-blocks of the particular block.

A nonvolatile semiconductor memory device includes a control circuit configured to control a soft program operation of setting nonvolatile memory cells to a first threshold voltage distribution state of the nonvolatile memory cells. When a characteristic of the nonvolatile memory cells is in a first state, the control circuit executes the soft program operation by applying a first voltage for setting the nonvolatile memory cells to the first threshold voltage distribution state to first word lines, and applying a second voltage higher than the first voltage to a second word line. When the characteristic of the nonvolatile memory cells is in a second state, the control circuit executes the soft program operation by applying a third voltage equal to or lower than the first voltage to the first word lines and applying a fourth voltage lower than the second voltage to the second word line.

A methodology and structure for driving a selected wordline to a negative voltage without the need for a negative wordline voltage generator. The methodology includes the step of boosting a non-selected wordline to a first positive voltage. The methodology proceeds with holding a selected wordline, which is adjacent to and capacitively coupled with the non-selected wordline, at zero voltage. The methodology continues with floating the selected wordline. The methodology proceeds with driving the non-selected wordline to a lower voltage to shift the selected wordline to less than zero volts due to capacitance effects. The methodology continues with the step of accelerating charge loss in a defective memory cell connected to the selected wordline while at a negative voltage during a soft erase operation.

A nonvolatile memory device includes a memory cell array, an erase body voltage generator, and an erase source voltage generator. The memory cell array includes memory blocks, each of which includes cell strings each including a ground selection transistor, memory cells, and a string selection transistor stacked in a direction perpendicular to a substrate. The erase body voltage generator applies an erase body voltage to the substrate during an erase operation. The erase source voltage generator applies an erase source voltage to a common source line connected with ground selection transistors of the cell strings during the erase operation.

According to the present embodiment, a nonvolatile semiconductor memory device includes a memory string group including k stacked memory strings, each of the memory strings including a plurality of nonvolatile memory cells connected in series, a selection transistor group including k selection transistors, each of the k selection transistors corresponding to each of the k memory strings respectively, the selection transistor group divided into n selection transistor sub-groups, each of the n selection transistor sub-groups including k/n selection transistors, n bit lines arranged in parallel to each of the k memory strings, and n bit line contacts arranged perpendicularly, each of the n bit line contacts connected to each of the n bit lines, respectively, each of the n bit line contacts connected to the k/n selection transistors belonging to the each of the n selection transistor sub-group respectively.

According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a control unit. The memory cell array includes a plurality of memory cells arranged in a matrix. The control unit erases data of the memory cells. The control unit interrupts the erase operation of the memory cells and holds an erase condition before the interrupt in accordance with a first command during the erase operation, and resumes the erase operation based on the held erase condition in accordance with a second command.

An operating method of a memory device including a plurality of strings on a substrate, wherein the plurality of strings include a main string connected to a bit line and a dummy string spaced apart from the bit line, the operating method including: pre-programming the dummy string; and erasing the main string and the dummy string, wherein the pre-programming includes: applying a pre-program voltage to a word line connected to the dummy string; applying a pass voltage to a ground selection line connected to a ground selection transistor of the dummy string; and applying a common source line voltage to a common source line connected to the dummy string.

An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to set an erase voltage for a first block of a persistent storage media to a default erase voltage, determine if the first block of the persistent storage media is identified for a secure erase operation, and set the erase voltage for the first block of the persistent storage media to a shallow erase voltage if the first block of the persistent storage media is identified for the secure erase operation, where the shallow erase voltage corresponds to a weaker erase operation relative to the default erase voltage. Other embodiments are disclosed and claimed.

A nonvolatile memory device includes a memory cell array, an erase body voltage generator, and an erase source voltage generator. The memory cell array includes memory blocks, each of which includes cell strings each including a ground selection transistor, memory cells, and a string selection transistor stacked in a direction perpendicular to a substrate. The erase body voltage generator applies an erase body voltage to the substrate during an erase operation. The erase source voltage generator applies an erase source voltage to a common source line connected with ground selection transistors of the cell strings during the erase operation.

According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a control unit. The memory cell array includes a plurality of memory cells arranged in a matrix. The control unit erases data of the memory cells. The control unit interrupts the erase operation of the memory cells and holds an erase condition before the interrupt in accordance with a first command during the erase operation, and resumes the erase operation based on the held erase condition in accordance with a second command.