The present disclosure relates to a method for improving the safety of the reading phase of a non-volatile memory device including at least an array of memory cells and with associated decoding and sensing circuitry and a memory controller, the method comprising:

storing in a dummy row of said memory block at least a known pattern;

performing some reading cycles changing the read trimming parameters up to the moment wherein said known value is read correctly;

adopting the trimming parameters of the correct reading for the subsequent reading phases.

The disclosure further relates to a memory device structured for implementing the above method.

The present disclosure provides a data storage control method, an electronic device, and a storage medium. The data storage control method includes obtaining lifespans of a plurality of memory blocks in a flash memory and selecting at least one target memory block according to the lifespans of the plurality of memory blocks, where the at least one target memory block is configured to store data to-be-written; determining a limit storage block with a shortest lifespan in the at least one target memory block; and outputting first prompt information according to the limit storage block and/or a lifespan of at least one memory block, where the first prompt information is configured to prompt lifespan information of the flash memory.

A memory sub-system configured to: measure a plurality of sets of signal and noise characteristics of a group of memory cells in a memory device; determine a plurality of optimized read voltages of the group of memory cells from the plurality of sets of signal and noise characteristics respectively; generate features from the plurality of sets of signal and noise characteristics, including at least one compound feature generated from the plurality of sets of signal and noise characteristics; generate, using the features, a classification of a bit error rate of data retrievable from the group of memory cells; and control an operation to read the group of memory cells based on the classification.

Systems, apparatus and methods are provided for performing program operations in a non-volatile storage system. In one embodiment, there is provided a method that may comprise categorizing active storage blocks of a non-volatile storage device into a robust group and a less-robust group based on a number of factors including page error count, program time and number of Program/Erase (P/E) cycles; determining that a cache program operation needs to be performed; selecting a first storage block from the robust group to perform the cache program operation; determining that a regular program operation needs to be performed; and selecting a second storage block from the less-robust group to perform the regular program operation.

The present disclosure relates to a method for improving the safety of the reading phase of a non-volatile memory device including at least an array of memory cells and with associated decoding and sensing circuitry and a memory controller, the method comprising: storing in a dummy row of said memory block at least a known pattern; performing some reading cycles changing the read trimming parameters up to the moment wherein said known value is read correctly; adopting the trimming parameters of the correct reading for the subsequent reading phases. The disclosure further relates to a memory device structured for implementing the above method.

Provided herein may be a memory device and a method of operating the same. The memory device may include a plurality of memory cells, a program operation performer configured to perform a plurality of program loops on the plurality of memory cells, a step voltage calculator configured to calculate a step voltage, the step voltage being a difference of magnitude between program voltages that are applied in any two consecutive program loops, a reference bit determiner configured to determine a reference number of fail bits based on a magnitude of the step voltage, and a verification result generator configured to generate verification result information based on a result of a comparison between the reference number of fail bits and a number of on-cells, among the plurality of memory cells, identified in a verify operation that is included in a program loop, among the plurality of program loops.

A temperature control method, a memory storage apparatus, and a memory control circuit unit are disclosed. The method includes: detecting a system parameter of the memory storage apparatus, and the system parameter reflects wear of a rewritable non-volatile memory module in the memory storage apparatus; determining a temperature control threshold value according to the system parameter; and performing a temperature reducing operation in response to a temperature of the memory storage apparatus reaching the temperature control threshold value to reduce the temperature of the memory storage apparatus.

A memory system includes a non-volatile memory having a plurality of memory cells and a controller. The controller is configured to switch a mode for controlling an access operation to the non-volatile memory from a first mode to a second mode, in response to receiving from a host, a first command for instructing the controller to switch the mode from the first mode to the second mode. The access operation controlled according to the second mode improves data retention relative to the access operation controlled according to the first mode.

A method includes determining that a ratio of valid data portions to a total quantity of data portions of a block of memory cells is greater than or less than a valid data portion threshold and determining that health characteristics for the valid data portions of the block of memory cells are greater than or less than a valid data health characteristic threshold. The method further includes performing a first media management operation on the block of memory cells in response to determining that the ratio of valid data portions to the total quantity of data portions is greater than the valid data portion threshold and performing a second media management operation on at least a portion of the block of memory cells in response to determining that the ratio of valid data portions to the total quantity of data portions is less than the valid data portion threshold and the health characteristics for the valid data portions are greater than the valid data health characteristic threshold.

A semiconductor memory device includes a memory cell array, a memory apparatus and a power-on operation apparatus, and is capable of knowing whether a reading of the setting information which is set during the power-on operation had been completed correctly or not. The flash memory reads the fuse memory when it is detected that the power supply has reached the power-on detection level, and determines whether the reading of the fuse memory had been completed correctly. When not completed correctly, the fuse memory is read again within the maximum read count, and the setting information (which was read from the fuse memory) is written into the CF register. The identification information (that identifies whether the reading of the fuse memory has been completed correctly or not) is stored in the register.