A data storage system can utilize one or more data storage devices that employ a solid-state non-volatile read destructive memory consisting of ferroelectric memory cells. A leveling strategy can be generated by a wear module connected to the memory with the leveling strategy prescribing a plurality of memory cell operating parameters associated with different amounts of cell wear. The wear module may monitor activity of a memory cell and detect an amount of wear in the memory cell as a result of the monitored activity, which can prompt changing a default set of operating parameters for the memory cell to a first stage of operating parameters, as prescribed by the leveling strategy, in response to the detected amount of wear.

A method for programming a memory block of a non-volatile memory structure, comprising determining whether a number of programming/erase cycles previously applied to the block exceeds a first programming/erase cycle threshold and, if the first threshold is exceeded, determining whether the number of programming/erase cycles previously applied to the block exceeds an extended programming/erase cycle threshold. Further, if the determination is made that the extended threshold is not exceeded, the method comprises applying a two-pulse per programming loop scheme to each of the outermost strings of the block and applying a single-pulse per programming loop scheme to all other strings of the block. Alternatively, or in addition thereto, relative to a programming/erase cycle threshold, one or more outermost strings of the block may be unpermitted to be further programmed, and a “sub-block” comprised of all valid strings of the block may be defined and permitted for further programming.

A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to one of a plurality of word lines and arranged in strings and configured to retain a threshold voltage corresponding to one of a plurality of memory states. A control circuit is coupled to the plurality of word lines and strings and is configured to erase the memory cells using a stripe erase operation in response to determining a cycle count is less than a predetermined cycle count maximum threshold. The control circuit is also configured to perform a dummy cycle operation in response to determining the cycle count is not less than the predetermined cycle count maximum threshold.

This disclosure proposes a method to save P/E cycling information inside NAND by using 2-byte column in programmable selective devices (e.g., SGD). The proposed method is a one-way programming method, and does not perform an erase operation within the 2-byte column. The proposed methods described herein can reduce the burden of relying upon controller SRAM/DRAM. Additionally, by storing the P/E cycling information in NAND, the P/E cycling is not lost due to a power loss event. At least one application advantageous for using NAND to store P/E cycling information includes wear leveling.

A method for dynamically adjusting an erase voltage level to be applied in a subsequent erase cycle, comprising: in a current erase cycle, initiating a current erase/verify loop by applying an initial stored erase voltage level according to an erase sequence in which each successive erase/verify loop is incremented by a pre-determined voltage amount, storing an erase/verify loop count, and determining whether the current erase cycle is complete according to a pass criterion. If the erase cycle is complete, a determination is made as to whether the stored erase/verify loop count equals a pre-defined threshold count. Further, if the stored count does not equal the pre-defined threshold count, the initial stored erase voltage level is adjusted such that, upon applying the adjusted erase voltage level in a subsequent erase cycle, an erase/verify loop count will now equal the pre-defined threshold count.

Technologies for scrambling functions in a column-addressable memory architecture includes a device having a memory and a circuitry. The memory includes a matrix storing individually addressable bit data, and the matrix is formed by rows and columns. The circuitry is to receive a request to perform a write operation of one or more bit values to one of the columns. The circuitry is further to determine a scrambler state at each location of the column, the location corresponding to a respective row and column index. The scrambler state is indicative of a function used to determine a value at the respective column location. Each of the bit values is scrambled as a function of the scrambler state for the respective column location and written thereto.

Methods, systems, and devices for adjustable programming pulses for a multi-level cell are described. A memory device may modify a characteristic of a programming pulse for an intermediate logic state based on a metric of reliability of associated memory cells. The modified characteristic may increase a read window and reverse a movement of a shifted threshold voltage distribution (e.g., by moving the threshold voltage distribution farther from one or more other voltage distributions). The metric of reliability may be determined by performing test writes may be a quantity of cycles of use for the memory cells, a bit error rate, and/or a quantity of reads of the first state. The information associated with the modified second pulse may be stored in fuses or memory cells, or may be implemented by a memory device controller or circuitry of the memory device.

A write cycle recording device includes a storage device and a controller. The storage device is corresponding to a memory block of a non-volatile memory. The storage device has a plurality of bits for recording a plurality of recorded writing loop counts corresponding to a plurality of writing operations of the memory block. The controller is configured to: perform a writing operation on the memory block; record a performed writing loop count of the writing operation; and, update a recorded writing loop count corresponding to the writing operation in the storage device according to the performed writing loop count.

A method includes determining that a ratio of valid data portions to a total quantity of data portions of a block of memory cells is greater than or less than a valid data portion threshold and determining that health characteristics for the valid data portions of the block of memory cells are greater than or less than a valid data health characteristic threshold. The method further includes performing a first media management operation on the block of memory cells in response to determining that the ratio of valid data portions to the total quantity of data portions is greater than the valid data portion threshold and performing a second media management operation on at least a portion of the block of memory cells in response to determining that the ratio of valid data portions to the total quantity of data portions is less than the valid data portion threshold and the health characteristics for the valid data portions are greater than the valid data health characteristic threshold.

Non-volatile memory systems and method for managing P/E cycling is disclosed. Memory systems include multi-plane (e.g., 2-plane or 4-plane) programming operations in which new blocks within a plane replace faulty/bad blocks. Existing blocks, having undergone several P/E cycles more than the new block(s), require a lower programming voltage and are programmed using an adaptive (reduced) programming voltage. New block(s) require an additional voltage, and a delta voltage is added to the programming voltage to increase the gate-to-channel voltage. To prevent the delta voltage from over-programming the existing blocks, a voltage equal to the delta voltage is applied bit lines of the existing blocks, thereby reducing the effective gate-to-channel voltage on the existing blocks. In this manner, the same programming voltage is applied to planes in a multi-plane programming operation, and the existing blocks receive a relatively lower gate-to-channel voltage, while the new block(s) receive a relatively higher gate-to-channel voltage.