An error correction system includes M decoding units, each configured to perform decoding on the X first operation codes and the Y second operation codes; the decoding unit includes: a decoder, configured to receive the X first operation codes and output N first decoded signals, each corresponding to a respective one bit of the N data; a first AND gate unit, configured to receive and perform a logical AND operation on Z selected operation codes; an NOR gate unit, configured to receive and perform a logical NOR operation on (Y−Z) unselected operation codes; and N second AND gate units, each having an input terminal connected to an output terminal of the first AND gate unit, an output terminal of the NOR gate unit and one of the first decoded signals.

Apparatuses and methods including a test circuit in a scribe region between chips are described. An example apparatus includes: a first semiconductor chip and a second semiconductor chip, adjacent to one another; a scribe region between the first and second semiconductor chips; test address pads in the scribe region; and an address decoder circuit in the scribe region. The test address pads receive address signals. The address decoder provides first signals responsive to the address signals from the test address pads.

A semiconductor device includes an error check and scrub (ECS) command generation circuit and an ECS control circuit. The ECS command generation circuit generates an ECS command based on a refresh command. During an ECS operation, the ECS control circuit generates an ECS mode signal that is activated based on the ECS command and generates an ECS active command, an ECS read command, and an ECS write command to continue the ECS operation.

Provided is a non-volatile storage system that performs error correction processing at high speed while ensuring error correction capability. When error correction decoding processing using data read first with hard-decision decoding processing has failed, a non-volatile storage device 2 reads data on the same page again, performs diversity synthesis processing on the readout data for the first time and the readout data for the second time on the same page as one for the first time, and then performs error correction processing using data after diversity synthesis processing.

A memory system according to an embodiment includes a memory device, and a memory controller. The memory device includes first and second memory cells, a first word line, and first and second bit lines. The first and second memory cells are provided in first and second layers, respectively. The first word line is coupled to the first memory cell and the second memory cell. The first bit line is coupled to the first memory cell. The second bit line is coupled to the second memory cell. The memory controller includes a storage circuit capable of storing a correction value table. The correction value table is configured to store a first correction value of a read voltage associated with the first layer and a second correction voltage of a read voltage associated with the second layer.

Systems and methods are provided for reading data from non-volatile storage devices and decoding the read data. A method may include obtaining a unique identifier for a storage location to be read, retrieving from a memory an adjustment to read reference voltage (Vref) associated with the unique identifier, performing a read operation on the storage location using a read reference voltage adjusted by the adjustment to Vref, decoding data read from the storage location in a decoding process and updating the adjustment to V.sub.ref in the memory with decoding information generated during the decoding process.

The present disclosure includes methods and apparatuses comprising a memory component having an independent structure and including an array of memory cells with associated decoding and sensing circuitry of a read interface, a host device coupled to the memory component through a communication channel, a JTAG interface in the array of memory cells, and an additional register in the JTAG interface. The additional register is configured to store a page address associated with the array of memory cells, the memory component is configured to load the page address at the power-on of the apparatus, and the host device is configured to perform a read sequence at the page address.

Example embodiments provide for a storage device that includes a storage controller including a plurality of analog circuits and at least one nonvolatile memory device including a first region and a second region. The at least one nonvolatile memory device stores user data in the second region and stores trimming control codes in the first region as a compensation data set. The trimming control codes are configured to compensate for offsets of the plurality of analog circuits and are obtained through a wafer-level test on the storage controller. The storage controller, during a power-up sequence, reads the compensation data set from the first region of the at least one nonvolatile memory device, stores the read compensation data set therein, and adjusts the offsets of the plurality of analog circuits based on the stored compensation data set.

A storage device includes a nonvolatile memory device and a memory controller to control the nonvolatile memory device. The nonvolatile memory device includes a memory cell array. The memory cell array includes a normal cell region, a parity cell region and a redundancy cell region. First bit-lines are connected to the normal cell region and the parity cell region and second bit-lines are connected to the redundancy cell region. The memory controller includes an error correction code (ECC) engine to generate parity data. The memory controller stores user data in the normal cell region, controls the nonvolatile memory device to perform a column repair on first defective bit-lines among the first bit-lines, assigns additional column addresses to the first defective bit-lines and the second bit-lines and stores at least a portion of the parity data in a region corresponding to the additionally assigned column addresses.

Systems and methods are provided for tracking read reference voltages used for reading data in a non-volatile storage device. A method may comprise collecting pre-decoding state information for a read reference voltage by reading data stored in a non-volatile storage device using the read reference voltage, collecting post-decoding state information for the read reference voltage after decoding the data, generating a comparison of probability of state errors for the read reference voltage based on the pre-decoding state information and post-decoding state information, obtaining an adjustment amount to the read reference voltage based on the comparison of probability of state errors; and adjusting the read reference voltage by applying the adjustment amount to the read reference voltage to obtain an adjusted read reference voltage.