A memory device comprises, on an integrated circuit or multi-chip module, a memory including a plurality of memory blocks, a controller, and a refresh mapping table in non-volatile memory accessible by the controller. The controller is coupled to the memory to execute commands with addresses to access addressed memory blocks in the plurality of memory blocks. The refresh mapping table has one or more entries, an entry in the refresh mapping table mapping of an address identifying an addressed memory block set for refresh to a backup block address. The controller is responsive to a refresh command sequence with a refresh block address to execute a refresh operation, and is configured to restore mapping of the refresh block address to the backup block address upon power-on of the device, to scan the refresh mapping table for a set entry, and to register the set entry in the refresh mapping table.

The present technology relates to a memory device and a method of operating the same. The memory device includes a memory block, a first page buffer group and a second page buffer group connected to bit lines of the memory block, and control logic configured to control the first page buffer group and the second page buffer group to perform a sense node precharge operation partially simultaneously.

The present technology relates to a memory device and a method of operating the same. The memory device includes a memory block, a first page buffer group and a second page buffer group connected to bit lines of the memory block, and control logic configured to control the first page buffer group and the second page buffer group to perform a sense node precharge operation partially simultaneously.

The present invention relates to a method of operating memory cells, comprising reading a previous user data from the memory cells; writing a new user data and merging the new user data with the previous user data into write registers; generating mask register information, and wherein the mask register information indicates bits of the previous user data stored in the memory cells to be switched or not to be switched in their logic values; counting numbers of a first logic value and a second logic value to be written using the mask register information, respectively; storing the numbers of the first logic value and the second logic value into a first counter and a second counter, respectively; and applying a programming pulse to the memory cells according to the mask register information.

According to one embodiment, a memory system manages a plurality of parallel units each including blocks belonging to different nonvolatile memory dies. When receiving from a host a write request designating a third address to identify first data to be written, the memory system selects one block from undefective blocks included in one parallel unit as a write destination block by referring to defect information, determines a write destination location in the selected block, and writes the first data to the write destination location. The memory system notifies the host of a first physical address indicative of both of the selected block and the write destination location, and the third address.

Methods, systems, and devices for adjustable column address scramble using fuses are described. A testing device may detect a first error in a first column plane of a memory array and a second error in a second column plane of the memory array. The testing device may identify a first column address of the first column plane associated with the first error and a second column address of the second column plane based on detecting the first error and the second error. The testing device may determine, for the first column plane, a configuration for scrambling column addresses of the first column plane to different column addresses of the first column plane. In some cases, the testing device may perform a fuse blow of a fuse associated with the first column plane to implement the determined configuration.

Aspects of the present disclosure relate to techniques for identifying susceptibility to induced charge leakage. In examples, a susceptibility test sequence comprising a cache line flush instruction is used to repeatedly activate a row of a memory unit. The susceptibility test sequence causes induced charge leakage within rows that are physically adjacent to the activated row, such that a physical adjacency map can be generated. In other examples, a physical adjacency map is used to identify a set of adjacent rows to a target row. A susceptibility test sequence is used to repeatedly activate the set of adjacent rows, after which the content of the target row is analyzed to determine whether the any bits of the target row flipped as a result of induced charge leakage. If flipped bits are not identified, an indication is generated that the memory unit is not susceptible to induced charge leakage.

A memory management method includes identifying memory segments of a memory device. The method also includes identifying, for each memory segment, a number of faulty columns and determining a total number of faulty columns for the memory device. The method also includes, in response to a determination that the total number of faulty columns is greater than a threshold, identifying a memory segment having a highest number of faulty columns. The method also includes disabling the memory segment. Another method includes identifying, for each memory segment, a number of faulty memory blocks and determining a total number of faulty memory blocks. The method also includes, in response to a determination that the total number of faulty memory blocks is greater than a threshold, identifying a memory segment having a highest number of faulty memory blocks. The method also includes disabling the memory segment.

Aspects of the present disclosure relate to techniques for identifying susceptibility to induced charge leakage. In examples, a susceptibility test sequence comprising a cache line flush instruction is used to repeatedly activate a row of a memory unit. The susceptibility test sequence causes induced charge leakage within rows that are physically adjacent to the activated row, such that a physical adjacency map can be generated. In other examples, a physical adjacency map is used to identify a set of adjacent rows to a target row. A susceptibility test sequence is used to repeatedly activate the set of adjacent rows, after which the content of the target row is analyzed to determine whether the any bits of the target row flipped as a result of induced charge leakage. If flipped bits are not identified, an indication is generated that the memory unit is not susceptible to induced charge leakage.

A processor memory is stress tested with a variable link stack depth using test code segments and link stack test segments on non-naturally aligned data boundaries. Link stack test segments are interspersed into test code segments of a processor memory test to change the link stack depth without changing results of the test code. The link stack test segments include branch to target, push/pop, push and pop segments. The depth of the link stack is varied independent of the memory test code by changing the number to branches in the branch to target segment and varying the number of the push/pop segments. The link stack test segments and test segments may be placed randomly with a recursive algorithm to intersperse the link stack test segments in the test code segments and to reduce the amount of data to be saved and restored for all subroutine calls, push and pop segments.