Testing systems and method of testing an integrated circuit are provided. A testing system comprises an input terminal, multiple circuit elements, each having a register, and an output terminal forming a scan chain through which an input signal is propagated. The testing system further comprises a debugger that includes a mapping module that stores information mapping register values to their respective functional meanings. The input signal is applied to extract all values of all of the registers whether or not accessible by a processor.

According to one embodiment, a memory system manages a plurality of parallel units each including blocks belonging to different nonvolatile memory dies. When receiving from a host a write request designating a third address to identify first data to be written, the memory system selects one block from undefective blocks included in one parallel unit as a write destination block by referring to defect information, determines a write destination location in the selected block, and writes the first data to the write destination location. The memory system notifies the host of a first physical address indicative of both of the selected block and the write destination location, and the third address.

Many error correction schemes fail to correct for double-bit errors and a module must be replaced when these double-bit errors occur repeatedly at the same address. This helps prevent data corruption. In an embodiment, the addresses for one of the memory devices exhibiting a single-bit error (but not the other also exhibiting a single bit error) is transformed before the internal memory arrays are accessed. This has the effect of moving one of the error prone memory cells to a different external (to the module) address such that there is only one error prone bit that is accessed by the previously double-bit error prone address. Thus, a double-bit error at the original address is remapped into two correctable single-bit errors that are at different addresses.

A memory-testing circuit configured to perform a test of reference bits in a memory. In a read operation, outputs of data bit columns are compared with one or more reference bit columns. The memory-testing circuit comprises: a test controller and association adjustment circuitry configurable by the test controller to associate another one or more reference bit columns or one or more data bit columns with the data bit columns in the read operation. The test controller can determine whether the original one or more reference bit columns have a defect based on results from the two different association.

Described apparatuses and methods enable a system including at least one memory device to load different address scramble patterns on dies of the memory device. The address scramble patterns may include the logical-to-physical conversion of rows in the memory device or the memory dies. In aspects, the apparatuses and methods can change the address scrambles at different intervals, such as after a power reset or when the data stored on the memory device is invalid, not current, flushable, or erasable. The described aspects may reduce effectiveness of usage-based disturb attacks used by malicious actors to discover a layout of a type of particular memory device or memory die.

To overcome a problem of increase of test time related to BIST in a conventional semiconductor device, a semiconductor device according to one embodiment includes a plurality of memory arrays having different sizes, a test pattern generation circuit that outputs a test pattern for the memory arrays, and a memory interface circuit that is provided for every memory array and converts an access address. The memory interface circuit shifts a test address output from the test pattern generation circuit in accordance with a shift amount set for every memory array, thereby converting the test address to an actual address of a memory array to be tested.

A semiconductor device includes a mode setting circuit configured to allocate any one of values to a mode signal based on an event signal, an address converter configured to generate a conversion address by converting at least one address based on the mode signal, and a memory circuit configured to perform an operation corresponding to the conversion address.

A semiconductor apparatus includes a semiconductor chip, with the semiconductor chip including a modular region and a test circuit. The modular region includes a plurality of modular areas each including a memory cell array with redundant bit lines and a peripheral memory area storing at least redundant addresses. The test circuit retrieves the redundant addresses intrinsic to the semiconductor chip. The distribution of the redundant addresses is randomly formed related to a part or an entirety of the modular area of the modular region. The distribution of the retrieved redundant addresses is irreversible, with a random number representing physical properties intrinsic to the semiconductor chip and providing copy protection. When another semiconductor chip uses the distribution of the retrieved redundant addresses the another semiconductor chip will malfunction. The test circuit outputs a random number generated from the distribution of the retrieved redundant addresses according to a specification code received from a physical-chip-identification measuring device.

The present application discloses a method for operating a memory device. The memory device includes a plurality of rows of repair one-time programmable (OTP) cells and a plurality of rows of main OTP cells. The method includes performing a testing procedure to determine validities of the plurality of rows of repair OTP cells and store repair information to a first part of rows of repair OTP cells that are determined to be valid, and performing a repairing procedure to determine validities of the plurality of rows of repair OTP cells and repair at least one row of main OTP cells that is determined to be invalid in the plurality of rows of main OTP by using a second part of the rows of repair OTP cells that are determined to be valid.

Methods, systems, and devices for bit retiring to mitigate bit errors are described. A memory device may retrieve a set of bits from a first row of an address space and may determine that the set of bits includes one or more errors. The memory device may remap at least a portion of the first row from a first row index to a second row index, where the second row index, before the remapping, corresponds to a second row within the address space addressable by the host device. Additionally or alternatively, the memory device may receive a first command to access a first logical address of a memory array that is associated with a first row index. The memory device may determine that the first row includes one or more errors and may transmit a signal indicating that the first row includes the one or more errors.