A schedulable memory scrubbing circuit and/or a known-state memory test circuit (collectively, background memory test apparatus (BGMTA)) are located on-chip with an integrated computing system. The BGMTA operates in parallel with a system CPU but shares a system bus with the CPU. The BGMTA sequentially reads one word at a time from a block of memory to be tested during system bus idle cycles. The schedulable memory scrubbing circuit embodiment tests on-chip parity/ECC memory arrays using memory controller-implemented parity or ECC error detection to trigger error handling interrupts. The known-state memory test circuit embodiment performs CRC calculations on known-state memory arrays as each data word is read sequentially. A final resulting CRC calculation value is compared to a known CRC value for the block, sometimes referred to as a golden CRC. If the two CRC values differ, a CRC error interrupt is triggered for servicing by the CPU.

A semiconductor memory apparatus may include a decoding unit configured to enable one of a plurality of sub word line driver enable signals by decoding a plurality of addresses while the decoding unit operates in a normal mode, and enables specific sub word line driver enable signals among the plurality of sub word line driver enable signals regardless of the plurality of addresses while the decoding unit is operating in a test mode. The semiconductor memory apparatus may include a sub word line driver group configured to include a plurality of sub word line drivers, the plurality of sub word line drivers configured for activation in response to the plurality of sub word line driver enable signals. The sub word line driver group is configured so that inactivated sub word line drivers are arranged between activated sub word line drivers while the decoding unit is operating in the test mode.

A failure analysis device is for analyzing a failure of the semiconductor device equipped with a logic circuit and a memory circuit. It has a storage device and a processor. The storage device stores fail bit data obtained by testing the memory circuit and failure diagnosis data obtained by failure diagnosis for test results of the logic circuit. The processor extracts the fail I/O value from the fail bit data, extracts the data of the memory connection port which is the connection port to the memory circuit from among the estimated failure parts included in the failure diagnosis data, and determines match/not-match between the fail I/O value and the port ID value included in the data of the memory connection port.

The disclosure relates to an electronic memory system, and more specifically, to a system to emulate an electrically erasable programmable read-only memory, and a method to emulate an electrically erasable programmable read-only memory. According to an embodiment of the disclosure, a system to emulate an electrically erasable programmable read-only memory is provided, the system including a first memory section and a second memory section, wherein the first memory section comprises a plurality of storage locations configured to store data partitioned into a plurality of data segments and wherein the second memory section is configured to store information mapping a physical address of a data segment stored in the first memory section to a logical address of the data segment.

Methods, systems, and devices for bit retiring to mitigate bit errors are described. A memory device may retrieve a set of bits from a first row of an address space and may determine that the set of bits includes one or more errors. The memory device may remap at least a portion of the first row from a first row index to a second row index, where the second row index, before the remapping, corresponds to a second row within the address space addressable by the host device. Additionally or alternatively, the memory device may receive a first command to access a first logical address of a memory array that is associated with a first row index. The memory device may determine that the first row includes one or more errors and may transmit a signal indicating that the first row includes the one or more errors.

A data processing apparatus includes configuration circuitry that receives, from software, a set of test information and configures each of a first storage circuit and a second storage circuit to perform a consistency test based on the test information. Check circuitry performs the consistency test between data stored in the first storage circuit and the second storage circuit and updates result storage circuitry with a result of the consistency test. The result storage circuitry is accessible to the software.

Many error correction schemes fail to correct for double-bit errors and a module must be replaced when these double-bit errors occur repeatedly at the same address. This helps prevent data corruption. In an embodiment, the addresses for one of the memory devices exhibiting a single-bit error (but not the other also exhibiting a single bit error) is transformed before the internal memory arrays are accessed. This has the effect of moving one of the error prone memory cells to a different external (to the module) address such that there is only one error prone bit that is accessed by the previously double-bit error prone address. Thus, a double-bit error at the original address is remapped into two correctable single-bit errors that are at different addresses.

A failure analysis device is for analyzing a failure of the semiconductor device equipped with a logic circuit and a memory circuit. It has a storage device and a processor. The storage device stores fail bit data obtained by testing the memory circuit and failure diagnosis data obtained by failure diagnosis for test results of the logic circuit. The processor extracts the fail I/O value from the fail bit data, extracts the data of the memory connection port which is the connection port to the memory circuit from among the estimated failure parts included in the failure diagnosis data, and determines match/not-match between the fail I/O value and the port ID value included in the data of the memory connection port.

The present application discloses a method for operating a memory device. The memory device includes a plurality of rows of repair one-time programmable (OTP) cells and a plurality of rows of main OTP cells. The method includes performing a testing procedure to determine validities of the plurality of rows of repair OTP cells and store repair information to a first part of rows of repair OTP cells that are determined to be valid, and performing a repairing procedure to determine validities of the plurality of rows of repair OTP cells and repair at least one row of main OTP cells that is determined to be invalid in the plurality of rows of main OTP by using a second part of the rows of repair OTP cells that are determined to be valid.

This document describes techniques, methods, and apparatuses for logical memory repair. In some aspects, a memory built-in self-test (MBIST) controller can perform logical memory repair for a memory cluster including a shared bus interface that is coupled to the MBIST controller and configured to provide access to multiple logical memories. The memory cluster includes multiple physical memories that are coupled to the shared bus interface. At least one physical memory is configured to have two or more logical memories overlaid thereon. In example aspects, the physical memory includes arbitration logic coupled to a first address register and a second address register that are respectively configured to store a first faulty memory address and a second faulty memory address. The arbitration logic includes circuitry configured to arbitrate access to at least one spare memory portion responsive to the first faulty memory address conflicting with the second faulty memory address.